PAC5220
Power Application Controller
12.4. Electrical Characteristics
Table 12-4. Gate Drivers Electrical Characteristics
(VP = 12V, VSYS = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Low-Side Gate Drivers (DRLx Pins)
VOH,DRL
VOL,DRL
IOHPK,DRL
IOLPK,DRL
High-Side Gate Drivers (DRHx, DRBx and DRSx Pins)
Repetitive, 10µs pulse
High-level output voltage
IDRLx = -50mA
VP−0.5
VP−0.25
V
V
A
A
Low-level output voltage
IDRLx = 50mA
0.175
-1
0.35
High-level pulsed peak source current 10µs pulse
Low-level pulsed peak sink current 10µs pulse
1
-5
0
53
52
65
64
16
VDRS
Level-shift driver source voltage range
V
V
Steady state
Repetitive, 10µs pulse
Steady state
5.2
5.2
5.2
VDRB
Bootstrap pin voltage range
VBS;DRB
Bootstrap supply voltage range
Bootstrap UVLO threshold
VDRBx, relative to respective VDRSx
V
V
VDRBx rising, relative to respective VDRSx
,Hysteresis= 1V
VUVLO;DRB
4.1
5.2
Gate Driver Disabled
Gate Driver Enabled
Gate Driver Disabled
Gate Driver Enabled
23
30
35
45
IBS;DRB
Bootstrap circuit supply current
Offset supply current
µA
µA
0.5
220
10
IOS;DRB
300
VDRBx
−0.25
VOH;DRH
High-level output voltage
Low-level output voltage
IDRHx = -50mA
IDRHx = 50mA
VDRBx−0.6
V
V
VDRSx
+0.175
VDRSx
+0.35
VOL;DRH
IOHPK;DRH
IOLPK;DRH
High-Side and Low-Side Gate Driver Propogation Delay
Delay setting 00
High-level pulsed peak source current 10µs pulse
-1
1
A
A
Low-level pulsed peak sink current 10µs pulse
10
50
ns
ns
ns
ns
Delay setting 01
Delay setting 10
Delay setting 11
tPD
Propagation Delay
120
250
- 41 -
Rev 1.5‒April 17, 2016
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
