PAC5220
Power Application Controller
low impedance and close gate shunt against coupling from the switch drain. These optional protection and slew
rate control are shown in Figure 12-3(b).
Figure 12-3. High-Side Switching Transients and Optional Circuitry
V
≤ 65V
DRBx
DRBx
V
P
V
IN
DRHx
DRSx
dV/dt
PAC5220
V
V
DRBx
dV/dt
DRLx
DRSx
V
≥ -5V
DRSx
(a) High-Side Switching Transients
(b) Optional Transient Protection and Slew Rate Control
12.3.4. Open-Drain Drivers
The OHIx pin can be configured to be a 40V/40mA or 40V/15mA open-drain driver output, or a logic input. When
configured as an open-drain driver output, the OHIx pin can be controlled by either a register bit or a
configurable digital signal matrix (CDSM) signal. With default polarity, the OHIx pin is switched to VSSP with
17.5Ω (40mA mode) or 50Ω (15mA mode) impedance in the on state when the corresponding bit or signal is '1',
and is in the high-impedance off state when the corresponding bit or signal is '0'. When configured as an input,
the OHIx pin signal can flow to a register bit or to a CDSM signal. The polarity bit determines the signal polarity
in both input and output modes.
12.3.5. Power Drivers Control
All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor
must first set the driver enable bit to '1'. The gate drivers are controlled by the microcontroller ports and/or PWM
signals according to Table 12-2, with configurable delays as shown in Table 12-3. The OHIx open-drain drivers
are controlled by their corresponding register bits. Refer to the PAC application notes and user guide for
additional information on power drivers control programming.
Table 12-2. Microcontroller Port and PWM to Power Driver Mapping
PWMA3/
PWMA4/
PWMB0
PART
NUMBER
PWMA5/
PWMC0
PWMA6/
PWMD0
PWMA0
PWMA1
PWMA2
PAC5220
DRL0
DRL1
DRL2
DRH3
DRH4
DRH5
- 39 -
Rev 1.5‒April 17, 2016
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
