PAC5220
Power Application Controller
13. ADC WITH AUTO-SAMPLING SEQUENCER
13.1. Block Diagram
Figure 13-1. ADC with Auto-Sampling Sequencer
ADC WITH AUTO-SAMPLING SEQUENCER
ADC RESULT REGISTERS
(16)
REGISTER
REGISTER
REGISTER
REGISTER
ADx
ADC
10-BIT
ADC
CONFIGURABLE ANALOG FRONT END
DIFFERENTIAL PGA
AUTO-SAMPLING
SEQUENCER
S/H
DAxP
DAxN
DIFF-PGA
STATE MACHINE 0
STATE MACHINE 1
EMUX CONTROL
V
, V , V /2
MON REF
TEMP
EMUX
13.2. Functional Description
13.2.1. ADC
The analog-to-digital converter (ADC) is a 10-bit succesive approximation register (SAR) ADC with 1 μs
conversion time and up to 1MSPS capability. The ADC input clock has a user-configurable divider from /1 to /8
of the system clock. The integrated analog multiplexer allows selection from up to 6 direct ADx inputs, and from
up to 10 analog inputs signals in the Configurable Analog Front End (CAFE), including up to 3 differential input
pairs. The ADC can be configured for repeating or non-repeating conversions and can interrupt the
microcontroller when a conversion is finished.
13.2.2. Auto-Sampling Sequencer
Two independent and flexible auto-sampling sequencer state machines allow signal sampling using the ADC
without interaction from microcontroller core. Each auto-sampling sequencer state machine can be programmed
to take and store up to 8 samples each in the ADC result register from different analog inputs, able to control the
ADC MUX and ADC Premux as well as the precise timing of the S/H in the Configurable analog front end. The
sampling start of the auto-sampling sequencer can be precisely triggered using timers A, B, C, or D or any of
their associated PWM edges (high-to-low or low-to-high). It also supports manual start or a ping-pong-scheme,
where one auto-sampling sequencer state machine triggers the other when it finishes sampling.
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Rev 1.5‒April 17, 2016
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
