PAC5220
Power Application Controller
Table 12-3. Power Driver Delay Configuration
DRLx
DRHx
FALLING
140ns
180ns
240ns
370ns
DELAY
SETTING
RISING
FALLING
140ns
RISING
160ns
200ns
260ns
380ns
00b Default Setting
01b Setting
130ns
170ns
230ns
360ns
180ns
10b Setting
250ns
11b Setting
380ns
12.3.6. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using protection signal from the Configurable
Analog Front End (CAFE), designated as protection event 1 (PR1) signal. The DRL0/DRL1/DRL2 drivers are
designated as low-side group 1. The DRH3/DRH4/DRH5 gate drivers are designated as high-side group 1. The
PR1 signal from the CAFE can be used to disable low-side group 1, high-side group 1, or both depending on the
PR1 mask bit settings.
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Rev 1.5‒April 17, 2016
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
