ACT8942
Rev 2, 15-Nov-12
Standby voltage could be preset to lower voltages
for SLEEP mode, the processor could assert VSEL
pin when entering SLEEP mode so that REG1 and
REG2 outputs switch to lower voltages to reduce
power consumption in SLEEP mode.
Disable Sequence
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before finally de-assert PWREN and PWRHLD,
disabling all regulators and shutting the system
down.
Waking up from SLEEP mode is typically initiated
when the user presses the push-button again,
which asserts nPBSTAT. Processors should
respond by asserting PWREN, which turns on
REG3, REG5, REG6 and REG7, and de-assert
VSEL so that REG1 and REG2 go back to normal
voltages, then normal operation may resume.
Figure 3:
Enable/Disable Sequence
ꢀ
ꢀ: Applicable only for ACT8942QJ2##.
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