ACT8942
Rev 2, 15-Nov-12
SYSTEM CONTROL INFORMATION
Interfacing with the Amlogic AML8726-M3
The ACT8942 is optimized for use in applications
using the Amlogic AML8726-M3 processor,
supporting both the power domains as well as the
signal interface for the processor.
the ACT8942 pin names and the AML8726-M3
processor pin names are provided. When this is
done, the AML8726-M3 pin names are located after
the ACT8942 pin names, and are italicized and
located inside parentheses. For example, PWREN
(GPIOAO_2) refers to the logic signal applied to the
ACT8942's PWREN input, identifying that it is
driven from the AML8726-M3’s GPIOAO_2 output.
Likewise, OUT1 (VCC1.2V_AO) refers to
ACT8942's OUT1 pin, identifying that it is
connected to the AML8726-M3’s VCC1.2V_AO
power domain.
While the ACT8942 supports many possible
configurations for powering these processors, one
of the most common configurations is detailed in
this datasheet. In general, this document refers to
the ACT8942 pin names and functions. However, in
cases where the description of interconnections
between these devices benefits by doing so, both
Table 2:
ACT8942 and Amlogic AML8726-M3 Power Domains
POWER DOMAIN
ACT8942 CHANNEL
TYPE
DEFAULT VOLTAGE
CURRENT CAPABILITY
VCC1.2V_AO
REG1
DC/DC
1.25V/1.25V
1150mA
VCC1.5V
VDDIO
REG2
REG3
REG4
DC/DC
DC/DC
LDO
1.5V/1.5V
3.0V/3.0V
3.0V
1150mA
1300mA
80mA
VDDIO_AO
AVDD3V
AVDD2.5V
HDMI_VCC
REG5
REG6
REG7
LDO
LDO
LDO
3.0V
2.5V
3.3V
320mA
320mA
320mA
Table 3:
ACT8942 and Amlogic AML8726-M3 Power Modes
POWER
QUIESCENT
CURRENT
CONTROL STATE
MODE
POWER DOMAIN STATE
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are on.
NORMAL
SLEEP
PWRHLD is asserted, PWREN is asserted.
PWRHLD is asserted, PWREN is de-asserted.
420µA
REG1, REG2 and REG4 are on, REG3,
REG5, REG6 and REG7 are off.
250µA
<18µA
SYSTEM
OFF
PWRHLD is de-asserted, PWREN is de-
asserted.
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are off.
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