ACT8942
Rev 2, 15-Nov-12
Amlogic AML8726-M3 application processor.
nRSTO Output
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires after
OUT4 reaches its power-OK threshold. When
asserted due to manual-reset, nRSTO immediately
asserts low, then remains asserted low until the
nPBIN input is de-asserted and the reset time-out
period expires.
Enabling/Disabling Sequence
A typical enable sequence is initiated whenever the
following conditions occurs:
1) nPBIN is asserted low via 50Kꢀ resistance, or
2) A valid input voltage is present at CHGINꢀ.
The enable sequence begins by enabling REG4.
When REG4 reaches its power-OK threshold,
nRSTO is asserted low, resetting the
microprocessor. REG1 is enabled after REG4
reaches its power-OK threshold for 2ms2, REG3 is
enabled after REG4 reaches its power-OK
threshold for 4ms2, REG2 is enabled after REG3
reaches its power-OK threshold for 2ms2, REG5,
REG6 and REG7 are enabled after REG3 reaches
its power-OK threshold for 4ms2. If REG4 is above
its power-OK threshold when the reset timer
expires, nRSTO is de-asserted, allowing the
microprocessor to begin its boot sequence.
Connect a 10kꢀ or greater pull-up resistor from
nRSTO to an appropriate voltage supply (typically
OUT4).
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kꢀ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
During the boot sequence, the microprocessor must
assert PWRHLD (GPIOAO_6), holding REG1,
REG2 and REG4, and assert PWREN
(GPIOAO_2), holding REG3, REG5, REG6 and
REG7 to ensure that the system remains powered
after nPBIN is released.
Many of the ACT8942's functions support interrupt-
generation as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
Once the power-up routine is completed, the
system remains enabled after the push-button is
released as long as both PWRHLD and PWREN is
asserted high. If the processor does not assert
PWRHLD before the user releases the push-button,
the boot-up sequence is terminated and all
regulators are disabled. This provides protection
against "false-enable", when the push-button is
accidentally depressed, and also ensures that the
system remains enabled only if the processor
successfully completes the boot-up sequence.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
Push-Button Control
The ACT8942 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWREN or PWRHLD) before nPBIN is de-asserted.
If the microprocessor is unable to complete its
power-up routine successfully before the user
releases the push-button, the ACT8942
automatically shuts the system down. This provides
protection against accidental or momentary
assertions of the push-button. If desired, longer
“push-and-hold” times can be implemented by
simply adding an additional time delay before
SLEEP Mode Sequence
The ACT8942 supports Amlogic AML8726-M3
processor’s SLEEP mode operation. Once a
successful power-up routine has been completed,
SLEEP mode may be initiated through a variety of
software-controlled mechanisms.
SLEEP mode is typically initiated when the user
presses the push-button during normal operation.
Pressing the push-button asserts the nPBIN input,
which asserts the nPBSTAT output, which
interrupts the processor. In response to this
interrupt the processor should de-assert PWREN,
disabling REG3, REG5, REG6 and REG7.
PWRHLD should remain asserted during SLEEP
mode so that REG1, REG2 and REG4 remain
enabled.
Control Sequences
The ACT8942 features
a
variety of control
sequences that are optimized for supporting system
enable and disable, as well as SLEEP mode of
ꢀ: Applicable only for ACT8942QJ2##.
ꢁ: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.
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