ACT8942
Rev 2, 15-Nov-12
SYSTEM CONTROL INFORMATION
Table 4:
ACT8942 and Amlogic AML8726-M3 Signal Interface
ACT8942
PWREN
SCL
DIRECTION
AMLOGIC AML8726-M3
GPIOAO_2
GPIOAO_4
GPIOAO_5
GPIOAO_3
Resetn
SDA
VSEL
nRSTO
nIRQ
GPIOAO_8
RTC_GPO
GPIOAO_6
nPBSTAT
PWRHLD
Table 5:
Control Pins
PIN NAME
OUTPUT
nPBIN
PWRHLD
PWREN
REG1, REG2, REG3, REG4, REG5, REG6, REG7
REG1, REG2, REG4
REG3, REG5, REG6, REG7
nPBSTAT Output
Control Signals
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage
(typically OUT4) through a 10kꢀ or greater resistor.
Enable Inputs
The ACT8942 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWREN, PWRHLD are logic inputs, while nPBIN is
a unique, multi-function input. Refer to Table 5 for a
description of which channels are controlled by
each input.
nPBIN Multi-Function Input
Figure 2:
ACT8942 features the nPBIN multi-function pin,
which combines system enable/disable control with
a hardware reset function. Select either of the two
pin functions by asserting this pin, either through a
direct connection to GA, or through a 50kꢀ resistor
to GA, as shown in Figure 2.
nPBIN Input
Manual Reset Function
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kꢀ).
When this occurs, nRSTO immediately asserts low,
then remains asserted low until the nPBIN input is
de-asserted and the reset time-out period expires.
ACT8942
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