ACT8935
Rev 4, 17-Sep-13
Figure 3:
Power Enable Sequence
Power Up Sequence
PBIN
nPBSTAT
260ms
nRSTO
PWREN
PWRHLD
OUT3
OUT5
93% of regulation
8ms
OUT1
OUT2
OUT4, OUT6, OUT7
REG3/PWRSTAT[ ]
SDREQ[ ]
DEEP-SLEEP Mode Sequence
SLEEP Mode Sequence
The ACT8935 supports Prima/Atlas IV DEEP-
SLEEP mode operation. Once a successful power-
up routine has been completed, DEEP-SLEEP
mode may be initiated through a variety of software-
controlled mechanisms.
The ACT8935 supports Prima/Atlas IV SLEEP
mode operation. Once a successful power-up
routine has been completed, SLEEP mode may be
initiated through a variety of software-controlled
mechanisms.
DEEP-SLEEP mode is typically initiated when the
user presses the push-button during normal
operation. Pressing the push-button asserts, the
nPBSTAT output, which interrupts the processor. In
response to this interrupt the processor should first
set the DSRDY[ ] bit to 1, then set the PWRDS[-] bit
to 1, disabling REG2, REG3, REG4, REG5, REG6,
and REG7.
The Prima and Atlas IV processors require that
REG3 is enabled by PBIN, but then operate
independently of PBIN in SLEEP mode. Therefore,
it is important that REG3/PWRSTAT[-] be set to 1
prior to entering SLEEP mode. This may be done
as part of the boot sequence or as part of the
sequence to enter SLEEP mode.
SLEEP mode is typically initiated when the user
presses the push-button during normal operation.
Pressing the push-button asserts, the nPBSTAT
output, which interrupts the processor. In response
to this interrupt the processor should de-assert
PWREN (X_PWR_EN), disabling REG3, REG4,
REG6 and REG7. PWRHLD should remain
asserted during SLEEP mode so that REG1, REG2
and REG5 remain enabled.
Waking from DEEP-SLEEP mode is initiated when
the user presses the push-button again. Asserting
PBIN clears the PWRDS[-] bit to 0, enabling REG3
and REG5. Once REG5 reaches regulation, REG2
is enabled and the nRSTO timer begins. Once the
reset timer period expires the nRSTO output is de-
asserted and the processor initiates a boot-up
sequence, during which it should determine the
system status by reading the DSRDY[-] bit; if the
value of DSRDY[-] is 0 then the software should
proceed with a typical enable sequence, whereas if
the value of DSRDY[-] is 1 then the software should
proceed with a “wake from DEEP-SLEEP” routine.
To complete the wake process, the processor should
assert PWRHLD to ensure that the system remains
enabled after the push-button is released, and assert
PWREN to enable REG4, REG6, and REG7, then set
DSRDY[-] to 0 to complete a full wake-up routine.
Waking from SLEEP mode is initiated when the
user presses the push-button again, which asserts
nPBSTAT. Processors should respond by asserting
PWREN (X_PWR_EN), which enables REG3,
REG4, REG6 and REG7, so that normal operation
may resume.
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