ACT8935
Rev 4, 17-Sep-13
APPLICATION INFORMATION
Interfacing with the SiRF PrimaTM/Atlas IVTM
The ACT8935 is optimized for use in applications
using the SiRF PrimaTM and Atlas IVTM processors,
supporting both the power domains as well as the
signal interface for these processors.
the ACT8935 pin names and the Prima/Atlas IV pin
names are provided. When this is done, the
Prima/Atlas IV pin names are located after the
ACT8935 pin names, and are italicized and located
inside parentheses. For example, PWREN
(X_PWR_EN) refers to the logic signal applied to
the ACT8935's PWREN input, identifying that it is
driven from the Prima/Atlas IV's X_PWR_EN
output. Likewise, REG2 (VDD_IO) refers to
ACT8935's OUT2 pin, identifying that it is
connected to the Prima/Atlas IV's VDD_IO power
domain.
While the ACT8935 supports many possible
configurations for powering these processors, one
of the most common configurations is detailed in
this datasheet. In general, this document refers to
the ACT8935 pin names and functions. However, in
cases where the description of interconnections
between these devices benefits by doing so, both
Table 2:
ACT8935 and SiRF Power Domains
SiRF POWER DOMAIN
VDDIO_MEM
VDD_IO
ACT8935 CHANNEL
REG1
TYPE
DC/DC
DC/DC
DC/DC
LDO
DEFAULT VOLTAGE
CURRENT CAPABILITY
900mA
1.8V
3.3V
1.2V
1.2V
1.2V
REG2
700mA
VDD_PDN/VDD_TSC
VDD_PLL
REG3
900mA
REG4
150mA
VDD_PRE
REG5
LDO
150mA
VREF_ADC
VDDA_TSC
REG6
LDO
LDO
2.5V
3.3V
150mA
150mA
VDD2V5_USB
VDD3V3_USB
REG7
Table 3:
ACT8935 and SiRF Power Modes
POWER MODE
CONTROL STATE
POWER DOMAIN STATE
QUIESCENT CURRENT
PWRHLD is asserted, PWREN is REG1, REG2, REG3, REG4, REG5,
ALL ON
420µA
asserted, PWRDS[ ] is 0
REG6 and REG7 are on
PWRHLD is asserted, PWREN is
de-asserted, PWRDS[ ] is 0
REG1, REG2 and REG5 are on.
REG3, REG4, REG6 and REG7 are off
SLEEP
260µA
155µA
PWRHLD is asserted, PWREN is
de-asserted, PWRDS[ ] is 1
REG1 is on. REG2, REG3, REG4,
REG5, REG6 and REG7 are off
DEEP-SLEEP
Table 4:
ACT8935 and SiRF Signal Interface
ACT8935
PWREN
SCL
DIRECTION
SiRF Prima / Atlas IV
X_PWR_EN
X_SCL_0
SDA
X_SDA_0
EXTON
nRSTO
nIRQ
X_RTC_Alarm
X_Reset_B
X_GPIO[1]1
X_GPIO[0]2
X_GPIO[4] ꢂ
X_VIP_PXD[6]ꢃ
GPIO5
nPBSTAT
nLBO
CHGLEV
PWRHLD
1, 2, ꢂ, ꢃ: Typical connections shown, actual connections may vary.
5: Optional connection for power hold control.
Innovative PowerTM
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