ACT8892
Rev 2, 01-Jul-15
GLOBAL REGISTER MAP
BITS
OUTPUT ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
NAME
DEFAULT
NAME
TRST nSYSMODE nSYSLEVMSK nSYSSTAT SYSLEV[3] SYSLEV[2] SYSLEV[1] SYSLEV[0]
SYS
0x00
0x01
0x20
0x21
0x22
0x30
0x31
0x32
0x40
0x41
0x42
0x50
0x51
0x54
0x55
0x60
0x61
0x64
0x65
0
1
0
R
0
1
1
1
Reserved FRC_ON1
Reserved
Reserved
SCRATCH SCRATCH HBRDY SCRATCH
SYS
DEFAULT
0
0
0
0
0
0
0
0
NAME
Reserved Reserved
VSET1[5]
VSET1[4]
VSET1[3] VSET1[2] VSET1[1] VSET1[0]
REG1
REG1
REG1
REG2
REG2
REG2
REG3
REG3
REG3
REG4
REG4
REG5
REG5
REG6
REG6
REG7
REG7
DEFAULT
NAME
DEFAULT
0
0
1
0
0
1
0
0
Reserved Reserved
VSET2[5]
VSET2[4]
VSET2[3] VSET2[2] VSET2[1] VSET2[0]
0
ON
0
0
PHASE
0
1
0
0
0
0
0
OK
R
NAME
MODE
DELAY[2]
DELAY[1] DELAY[0] nFLTMSK
DEFAULT
NAME
DEFAULT
0
0
0
1
0
Reserved Reserved
VSET1[5]
VSET1[4]
VSET1[3] VSET1[2] VSET1[1] VSET1[0]
0
0
1
1
0
1
1
0
NAME
Reserved Reserved
VSET2[5]
VSET2[4]
VSET2[3] VSET2[2] VSET2[1] VSET2[0]
DEFAULT
NAME
DEFAULT
0
ON
0
0
PHASE
0
1
1
0
1
1
0
OK
R
MODE
DELAY[2]
DELAY[1] DELAY[0] nFLTMSK
0
0
1
0
0
NAME
Reserved Reserved
VSET1[5]
VSET1[4]
VSET1[3] VSET1[2] VSET1[1] VSET1[0]
DEFAULT
NAME
DEFAULT
0
0
0
1
1
0
0
0
Reserved Reserved
VSET2[5]
VSET2[4]
VSET2[3] VSET2[2] VSET2[1] VSET2[0]
0
ON
0
0
PWRSTAT
0
0
0
1
1
1
0
NAME
MODE
DELAY[2]
DELAY[1] DELAY[0] nFLTMSK
OK
DEFAULT
NAME
DEFAULT
0
0
1
VSET[3]
0
1
VSET[2]
1
0
VSET[1]
0
R
Reserved Reserved
VSET[5]
VSET[4]
VSET[0]
0
ON
0
0
DIS
1
1
1
0
NAME
LOWIQ
DELAY[2]
DELAY[1] DELAY[0] nFLTMSK
OK
DEFAULT
NAME
DEFAULT
0
0
1
VSET[3]
1
0
VSET[2]
0
0
VSET[1]
0
R
Reserved Reserved
VSET[5]
VSET[4]
VSET[0]
0
ON
0
0
DIS
1
1
1
1
NAME
LOWIQ
DELAY[2]
DELAY[1] DELAY[0] nFLTMSK
OK
DEFAULT
NAME
DEFAULT
0
0
1
VSET[3]
0
0
VSET[2]
1
0
VSET[1]
1
R
Reserved Reserved
VSET[5]
VSET[4]
VSET[0]
0
ON
0
0
DIS
1
1
1
0
NAME
LOWIQ
DELAY[2]
DELAY[1] DELAY[0] nFLTMSK
OK
DEFAULT
NAME
DEFAULT
0
VSET[5]
0
0
1
VSET[3]
1
0
VSET[2]
1
0
VSET[1]
1
R
VSET[0]
0
Reserved Reserved
VSET[4]
0
ON
0
0
DIS
1
1
DELAY[2]
0
NAME
DEFAULT
LOWIQ
0
DELAY[1] DELAY[0] nFLTMSK
OK
1
0
0
R
: Default values of ACT8892Q4I134-T.
: All bits are automatically cleared to default values when the input power is removed or falls below the system UVLO.
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