ACT8892
Rev 2, 01-Jul-15
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
1
OUT1
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1,GP2 and GP3
together at a single point as close to the IC as possible.
2
3
GA
Output Voltage for REG4. Capable of delivering up to 320mA of output current. Connect a 3.3µF
ceramic capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when
disabled.
OUT4
Output Voltage for REG5. Capable of delivering up to 320mA of output current. Connect a 3.3µF
ceramic capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when
disabled.
4
OUT5
Power Input for REG4 and REG5. Bypass to GA with a high quality ceramic capacitor placed as
close to the IC as possible.
5
6
INL45
INL67
Power Input for REG6 and REG7. Bypass to GA with a high quality ceramic capacitor placed as
close to the IC as possible.
Output Voltage for REG6. Capable of delivering up to 320mA of output current. Connect a 3.3µF
ceramic capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when
disabled.
7
8
9
OUT6
OUT7
nPBIN
Output Voltage for REG7. Capable of delivering up to 320mA of output current. Connect a 3.3µF
ceramic capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when
disabled.
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive nPBIN
directly to GA to assert a manual reset condition. Refer to the nPBIN Multi-Function Input section
for more information. nPBIN is internally pulled up to VVDDREF through a 35kΩ resistor.
10
11
PWRHLD Power Hold Input. Refer to the Control Sequences section for more information.
nRSTO
nIRQ
Active Low Reset Output. See the nRSTO Output section for more information.
Open-Drain Interrupt Output. nIRQ asserts any time an unmasked fault condition exists or an
interrupt occurs. See the nIRQ Output section for more information.
12
13
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the
nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information.
nPBSTAT
Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to
the IC as possible.
14
15
16
GP3
SW3
VP3
Switching Node Output for REG3. Connect this pin to the switching end of the inductor.
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the
IC as possible.
17
18
PWREN Power Enable Input. Refer to the Control Sequences section for more information.
NC1
Not Connected. Not internally connected.
Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
19
20
OUT3
Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage. See the Output Voltage Programming
section for more information.
VSEL
SCL
SDA
Clock Input for I2C Serial Interface.
21
22
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
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