ACT8892
Rev 2, 01-Jul-15
REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Reset Timer Setting. Defines the reset timeout threshold. See
nRSTO Output section for more information.
SYS
SYS
0x00
0x00
[7]
TRST
R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Generate an interrupt when VVDDREF falls
below the programmed SYSLEV threshold, 0: automatic
shutdown when VVDDREF falls below the programmed SYSLEV
threshold.
[6] nSYSMODE
R/W
System Voltage Level Interrupt Mask. Disabled interrupt by
default, set to 1 to enable this interrupt. See the Programmable
System Voltage Monitor section for more information
SYS
SYS
0x00
0x00
[5] nSYSLEVMSK R/W
System Voltage Status. Value is 1 when VVDDREF is lower than the
SYSLEV voltage threshold, value is 0 when VVDDREF is higher
than the system voltage detection threshold.
[4]
nSYSSTAT
R
System Voltage Detect Threshold. Defines the SYSLEV voltage
threshold. See the Programmable System Voltage Monitor
section for more information.
SYS
SYS
SYS
SYS
SYS
0x00
0x01
0x01
0x01
0x01
[3:0]
[7]
SYSLEV
R/W
R
-
Reserved.
Force-On bit for REG1. Set bit to 1 before entering Hibernate
mode to keep REG1 ON during Hibernate. Clear bit to 0 after
waking from Hibernate mode.
[6]
FRC_ON1
R/W
R
[5:4]
-
Reserved.
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
upon system shutdown.
[3:2] SCRATCH
R/W
Hibernate Ready Flag. Set bit to 1 before entering Hibernate
mode, then read this bit during enable sequence to identify
system status: if bit value is 1 the system is waking from
Hibernate mode, if bit value is 0 the system is waking from a
disabled state.
SYS
0x01
[1]
HBRDY
R/W
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
upon system shutdown.
SYS
0x01
0x20
0x20
0x21
0x21
[0]
SCRATCH
R/W
R
REG1
REG1
REG1
REG1
[7:6]
[5:0]
[7:6]
[5:0]
-
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information.
VSET1
-
R/W
R
Reserved.
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
VSET2
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1
REG1
0x22
0x22
[7]
[6]
ON
R/W
R/W
Regulator Phase Control. Set bit to 1 for regulator to operate
180° out of phase with the oscillator, clear bit to 0 for regulator to
operate in phase with the oscillator.
PHASE
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-savings
mode under light-load conditions.
REG1
0x22
[5]
MODE
R/W
Regulator Turn-On Delay Control. See the REG1, REG2, REG3
Turn-on Delay section for more information.
REG1
REG1
0x22
0x22
[4:2]
[1]
DELAY
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
nFLTMSK
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