ACT5880
Rev 2, 03-Sep-13
GLOBAL REGISTER MAP
BITS NAMES AND DEFAULTS
FUNCTION
ADDR.
BLOCK
D7
TRST
0
D6
D5
D4
D3
D2
SYSLEV[2]
0
D1
SYSLEV[1]
0
D0
SYSLEV[0]
0
nSYSMODE nSYSLVMSK nSYSSTAT SYSLEV[3]
SYS
SYS
0x00
0x01
0
EVENT2
0
0
EVENT4
0
R
RFU
0
0
EVENT1
0
SCRATCH[3] SCRATCH[2] SCRATCH[1] SCRATCH[0]
x
x
x
x
Set to 0x80 before setting nWKALM and RAAI.
Set to 0x08 before setting nWKALM and RAAI.
SYS
SYS
0x3C
0x3D
RFU
RFU
STB
STA
RFU
RFU
DATAB
DATAA
SYS
0x6C
0x6D
0x10
0x11
0x12
0x20
0x22
0x28
0x29
0x30
0x31
0x40
0x41
0x44
0x45
x
x
0
1
x
x
0
0
RFU
RFU
POSB
POSA
RFU
RFU
NEGB
RFU
SYS
x
x
0
1
x
x
0
x
x
x
VSET0[5]
VSET0[4]
VSET0[3]
VSET0[2]
VSET0[1]
VSET0[0]
REG1
REG1
REG1
REG2
REG2
REG2
REG2
REG3
REG3
REG4
REG4
REG5
REG5
0
0
0
1
1
0
0
0
x
x
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
0
0
0
1
1
0
0
0
ON
PHASE
MODE
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
1
0
0
0
0
0
0
R
x
x
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
1
0
0
1
0
0
ON
PHASE
MODE
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
1
1
0
0
0
0
0
R
x
x
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
1
0
0
1
0
0
x
x
LOWIQ
x
x
x
nFLTMSK
OK
1
0
1
0
0
0
0
R
VSET[7]
VSET[6]
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
ON
0
1
0
1
0
1
0
0
PHASE
RFU
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
x
0
0
0
0
0
R
x
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
1
1
0
1
0
1
ON
1
DIS
0
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
VSET[5]
1
0
0
0
0
R
x
x
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
1
DELAY[2]
0
0
DELAY[1]
0
1
DELAY[0]
0
0
nFLTMSK
0
1
OK
R
ON
1
DIS
0
LOWIQ
0
Cont'd in next page.
Note:
SYS: The registers for the system control block; REG1 to REG5: The registers for regulators that generate the OUT1 to
OUT5.
RTC: The registers for Real Time Clock block.
RFU is the bit reserved for future use. R: Read accessible, writing to the bit does not make change to the volume. X is
uncertain volume.
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