ACT5880
Rev 2, 03-Sep-13
PIN DESCRIPTIONS
PIN
E8
NAME
SW2
DESCRIPTION
The Switch Node of the Step-down DC/DC REG2. Same function as pin E9.
The Switch Node of the Step-down DC/DC REG2. Same function as pin E8.
E9
SW2
The Ground Path of the Step-down DC/DC REG1. Provide the direct ground return path between
the internal switch, the external storage capacitor and the input decoupling capacitor. Same function
as pin G3.
F1
F2
GP1
The Open Drain Output 1. A current driver output with programmable output current. It could operate
in constant current mode, switch on/off mode or PWM mode. The maximum voltage is 40V for this
pin.
ODO1
F3
F4
OUT13
The Output of the LDO REG13. Bypass to GA with a 1.5μF high quality ceramic capacitor.
The Input Node for the LDO REG12 and REG13. Bypass to GA with a 1μF high quality ceramic
capacitor.
INL1213
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1, GP2 and GP3 to a
single point as close to the IC as possible.
F5
F6
GA
The Reference Bypass Node. Bypass to GA with a 47nF capacitor for noise suppression and PSRR
performance improvement. This pin is discharged to GA in shutdown.
REFBP
F7
F8
F9
G1
G2
G3
G4
OUT2
VP2
The Step-down DC/DC REG2 Feedback Node. Connect it to the output node of REG2.
The Switch Power Input Node of the Step-down DC/DC REG2. Same function as pin F9.
The Switch Power Input Node of the Step-down DC/DC REG2. Same function as pin F8.
The Switch Node of the Step-down DC/DC REG1. Same function as pin G2 and pin H1.
The Switch Node of the Step-down DC/DC REG1. Same function as pin G1 and pin H1.
The Ground Path of the Step-down DC/DC REG1. Same function as pin F1.
VP2
SW1
SW1
GP1
OUT12
The Output of the LDO REG12. Bypass to GA with a 2.2μF high quality ceramic capacitor.
The Internal Bias Bypass. This rail is available all time that this IC works, bypass to GA with a 1μF
high quality ceramic capacitor.
G5
G6
G7
G8
G9
VSYS
VD
The Power Input for Biasing the ADC Circuit. Bypass to GD with a 100nF high quality ceramic
capacitor.
One of ADC Input, Internally Configured as the Touch Screen Force-Sense Node XNEG with an
internal force switch.
XNEG
YPOS
YNEG
One of ADC Input, Internally Configured as the Touch Screen Force-Sense Node YPOS with an
internal force switch.
One of ADC Input, Internally Configured as the Touch Screen Force-Sense Node YNEG with an
internal force switch.
H1
H2
SW1
VP1
The Switch Node of the Step-down DC/DC REG1. Same function as pin G1 and pin G2.
The Switch Power Input Node of the Step-down DC/DC REG1. Same function as pin J2.
The Output Voltage Selection Input for the Step-down DC/DC REG1. Allow the output voltage of the
step-down DC/DC REG1 flies between 2 preset voltages by asserting different logic level at this pin.
H3
H4
H5
VSEL
SCL
The Clock for the I2C compatible Serial Interface. Does the same function as the SCL of a normal
400kHz fast I2C slave device.
The Data for the I2C compatible Serial Interface. Does the same function as the SDA of a normal
400kHz fast I2C slave device.
SDA
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