PLUS
ProASIC
Flash Family FPGAs
Package Pins
Physical I/O
Buffers
Global MUX
Configuration Tile
GL
Std. Pad Cell
PECL Pad Cell
Global MUX B
OUT
NPECL
PPECL
External
Feedback
Global MUX A
OUT
GLMX
GL
Std. Pad Cell
Std. Pad Cell
Configuration Tile
CORE
Legend
Physical Pin
DATA Signals to the Global MUX
DATA Signals to the Core
Control Signals to the Global MUX
DATA Signals to the PLL Block
Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time.
Figure 1-15 • Input Connectors to ProASICPLUS Clock Conditioning Circuitry
Table 1-7 • Clock-Conditioning Circuitry MUX Settings
MUX
Datapath
Comments
FBSEL
1
Internal Feedback
2
Internal Feedback and Advance Clock Using FBDLY
External Feedback (EXTFB)
–0.25 to –4 ns in 0.25 ns increments
3
XDLYSEL
0
Feedback Unchanged
1
Deskew feedback by advancing clock by system delay
GLB
Fixed delay of -2.95 ns
OBMUX
0
Primary bypass, no divider
Primary bypass, use divider
Delay Clock Using FBDLY
Phase Shift Clock by 0°
Phase Shift Clock by +90°
Phase Shift Clock by +180°
Phase Shift Clock by +270°
GLA
1
2
+0.25 to +4 ns in 0.25 ns increments
4
5
6
7
OAMUX
0
1
2
3
Secondary bypass, no divider
Secondary bypass, use divider
Delay Clock Using FBDLY
Phase Shift Clock by 0°
+0.25 to +4 ns in 0.25 ns increments
v5.2
1-15
ACTEL [ Actel Corporation ]
