PLUS
ProASIC
Flash Family FPGAs
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles. The TRST pin
may also be used to asynchronously place the TAP
controller in the Test-Logic-Reset state.
ProASICPLUS devices support three types of test data
registers: bypass, device identification, and boundary
scan. The bypass register is selected when no other
register needs to be accessed in a device. This speeds up
test data transfer to other devices in a test data path.
The 32-bit device identification register is a shift register
with four fields (lowest significant byte (LSB), ID number,
part number and version). The boundary-scan register
observes and controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary-
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output, and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Test-Logic
1
Reset
0
1
0
1
0
1
Run-Test/
Idle
Select-DR-
Scan
Select-IR-
Scan
0
0
0
Capture-DR
0
Capture-IR
0
1
1
Shift-IR
1
Shift-DR
1
1
1
Exit-DR
Exit-IR
0
Pause-DR
1
0
Pause-IR
1
0
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
0
0
1
1
Figure 1-13 • TAP Controller State Diagram
1-12
v5.2
ACTEL [ Actel Corporation ]
