PLUS
ProASIC
Flash Family FPGAs
two signals available to drive the global networks are as
follows (Figure 1-15 on page 1-15, Table 1-7 on page 1-
15, and Table 1-8 on page 1-16):
Timing Control and
Characteristics
Global A (secondary clock)
PLUS
ProASIC
Clock Management System
•
Output from Global MUX A
ProASICPLUS devices provide designers with very flexible
clock conditioning capabilities. Each member of the
ProASICPLUS family contains two phase-locked loop (PLL)
blocks which perform the following functions:
•
Conditioned version of PLL output (fOUT) – delayed
or advanced
•
•
Divided version of either of the above
Further delayed version of either of the above
(0.25 ns, 0.50 ns, or 4.00 ns delay)1
•
Clock Phase Adjustment via Programmable Delay
(250 ps steps from –7 ns to +8 ns)
Global B
•
•
Clock Skew Minimization
Clock Frequency Synthesis
•
•
•
•
Output from Global MUX B
Delayed or advanced version of fOUT
Divided version of either of the above
Further delayed version of either of the above
(0.25 ns, 0.50 ns, or 4.00 ns delay)2
Each PLL has the following key features:
•
•
Input Frequency Range (fIN) = 1.5 to 180 MHz
Feedback Frequency Range (fVCO
) = 1.5 to
180 MHz
Functional Description
Each PLL block contains four programmable dividers as
shown in Figure 1-14 on page 1-14. These allow
frequency scaling of the input clock signal as follows:
•
•
•
•
Output Frequency Range (fOUT) = 6 to 180 MHz
Output Phase Shift = 0 °, 90 °, 180 °, and 270 °
Output Duty Cycle = 50%
Low Output Jitter (max at 25°C)
•
The n divider divides the input clock by integer
factors from 1 to 32.
–
–
–
f
VCO <10 MHz. Jitter 1% or better
10 MHz < fVCO < 60 MHz. Jitter 2% or better
VCO > 60 MHz. Jitter 1% or better
•
The m divider in the feedback path allows
multiplication of the input clock by integer factors
ranging from 1 to 64.
f
Note: Jitter(ps) = Jitter(%)* period
•
•
The two dividers together can implement any
combination of multiplication and division
resulting in a clock frequency between 24 and 180
MHz exiting the PLL core. This clock has a fixed
50% duty cycle.
The output frequency of the PLL core is given by
the formula EQ 1-1 (fREF is the reference clock
frequency):
For Example:
Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps
•
•
Maximum Acquisition = 80 µs for fVCO > 40 MHz
Time
= 30 µs for fVCO < 40 MHz
Low Power Consumption – 6.9 mW (max – analog
fOUT = fREF * m/n
supply) + 7.0µW/MHz (max – digital supply)
EQ 1-1
Physical Implementation
•
The third and fourth dividers (u and v) permit the
signals applied to the global network to each be
further divided by integer factors ranging from 1
to 4.
Each side of the chip contains a clock conditioning circuit
based on a 180 MHz PLL block (Figure 1-14 on page 1-
14). Two global multiplexed lines extend along each side
of the chip to provide bidirectional access to the PLL on
that side (neither MUX can be connected to the opposite
side's PLL). Each global line has optional LVPECL input
pads (described below). The global lines may be driven
by either the LVPECL global input pad or the outputs
from the PLL block, or both. Each global line can be
driven by a different output from the PLL. Unused global
pins can be configured as regular I/Os or left
unconnected. They default to an input with pull-up. The
The implementations shown in EQ2 and EQ3 enable the
user to define a wide range of frequency multiplier and
divisors.
fGLB = m/(n*u)
EQ 1-2
fGLA = m/(n*v)
EQ 1-3
1. This mode is available through the delay feature of the Global MUX driver.
v5.2
1-13
ACTEL [ Actel Corporation ]
