Device Architecture
SRAM and FIFO
All Fusion devices have SRAM blocks along the north side of the device. Additionally, AFS600 and
AFS1500 devices have an SRAM block on the south side of the device. To meet the needs of high-
performance designs, the memory blocks operate strictly in synchronous mode for both read and
write operations. The read and write clocks are completely independent, and each may operate at
any desired frequency less than or equal to 350 MHz. The following configurations are available:
•
•
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4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—two read, two write or one read, one write)
512×9, 256×18 (two-port RAM—one read and one write)
Sync write, sync pipelined/nonpipelined read
The Fusion SRAM memory block includes dedicated FIFO control logic to generate internal
addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY).
During RAM operation, addresses are sourced by the user logic, and the FIFO controller is ignored.
In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM
array by internal MUXes. Refer to Figure 2-46 for more information about the implementation of
the embedded FIFO controller.
The Fusion architecture enables the read and write sizes of RAMs to be organized independently,
allowing for bus conversion. This is done with the WW (write width) and RW (read width) pins. The
different D×W configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1. For example, the write size
can be set to 256×18 and the read size to 512×9.
Both the write and read widths for the RAM blocks can be specified independently with the WW
(write width) and RW (read width) pins. The different D×W configurations are 256×18, 512×9,
1k×4, 2k×2, and 4k×1.
Refer to the allowable RW and WW values supported for each of the RAM macro types in
Table 2-27 on page 2-61.
When a width of one, two, or four is selected, the ninth bit is unused. For example, when writing 9-
bit values and reading 4-bit values, only the first four bits and the second four bits of each 9-bit
value are addressable for read operations. The ninth bit is not accessible.
2-58
Preliminary v1.7
ACTEL [ Actel Corporation ]
