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AFS600-2FGG256I 参数 Datasheet PDF下载

AFS600-2FGG256I图片预览
型号: AFS600-2FGG256I
PDF下载: 下载PDF文件 查看货源
内容描述: Actel的Fusion混合信号FPGA [Actel Fusion Mixed-Signal FPGAs]
分类和应用:
文件页数/大小: 318 页 / 10484 K
品牌: ACTEL [ Actel Corporation ]
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Device Architecture  
Flash Memory Block Characteristics  
CLK  
RESET  
Active Low, Asynchronous  
BUSY  
Figure 2-43 • Reset Timing Diagram  
Table 2-25 • Flash Memory Block Timing  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
Description  
–2  
–1  
Std.  
10.70  
6.74  
6.62  
5.96  
Units  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLK2RD  
Clock-to-Q in 5-cycle read mode of the Read Data  
Clock-to-Q in 6-cycle read mode of the Read Data  
Clock-to-Q in 5-cycle read mode of BUSY  
Clock-to-Q in 6-cycle read mode of BUSY  
Clock-to-Status in 5-cycle read mode  
7.99  
5.03  
4.95  
4.45  
9.10  
5.73  
5.63  
5.07  
tCLK2BUSY  
tCLK2STATUS  
11.24 12.81 15.06  
Clock-to-Status in 6-cycle read mode  
4.48  
1.92  
0.00  
2.76  
0.00  
1.85  
0.00  
3.85  
0.00  
2.37  
0.00  
2.16  
0.00  
3.74  
0.00  
3.74  
0.00  
2.17  
0.00  
3.76  
0.00  
2.01  
0.00  
5.10  
2.19  
0.00  
3.14  
0.00  
2.11  
0.00  
4.39  
0.00  
2.69  
0.00  
2.46  
0.00  
4.26  
0.00  
4.26  
0.00  
2.47  
0.00  
4.28  
0.00  
2.29  
0.00  
6.00  
2.57  
0.00  
3.69  
0.00  
2.48  
0.00  
5.16  
0.00  
3.17  
0.00  
2.89  
0.00  
5.01  
0.00  
5.00  
0.00  
2.90  
0.00  
5.03  
0.00  
2.69  
0.00  
tDSUNVM  
Data Input Setup time for the Control Logic  
Data Input Hold time for the Control Logic  
Address Input Setup time for the Control Logic  
Address Input Hold time for the Control Logic  
Data Width Setup time for the Control Logic  
Data Width Hold time for the Control Logic  
Read Enable Setup time for the Control Logic  
Read Enable Hold Time for the Control Logic  
Write Enable Setup time for the Control Logic  
Write Enable Hold Time for the Control Logic  
Program Setup time for the Control Logic  
Program Hold time for the Control Logic  
SparePage Setup time for the Control Logic  
SparePage Hold time for the Control Logic  
Auxiliary Block Setup Time for the Control Logic  
Auxiliary Block Hold Time for the Control Logic  
ReadNext Setup Time for the Control Logic  
ReadNext Hold Time for the Control Logic  
Erase Page Setup Time for the Control Logic  
Erase Page Hold Time for the Control Logic  
Unprotect Page Setup Time for the Control Logic  
Unprotect Page Hold Time for the Control Logic  
tDHNVM  
tASUNVM  
tAHNVM  
tSUDWNVM  
tHDDWNVM  
tSURENNVM  
tHDRENNVM  
tSUWENNVM  
tHDWENNVM  
tSUPROGNVM  
tHDPROGNVM  
tSUSPAREPAGE  
tHDSPAREPAGE  
tSUAUXBLK  
tHDAUXBLK  
tSURDNEXT  
tHDRDNEXT  
tSUERASEPG  
tHDERASEPG  
tSUUNPROTECTPG  
tHDUNPROTECTPG  
2-54  
Preliminary v1.7  
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