Actel Fusion Mixed-Signal FPGAs
Conversely, when writing 4-bit values and reading 9-bit values, the ninth bit of a read operation
will be undefined. The RAM blocks employ little-endian byte order for read and write operations.
RD
RD[17:0]
WD[17:0]
RCLK
WD
RCLK
WCLK
WCLK
RAM
RADD[J:0]
WADD[J:0]
REN
WEN
FREN
FWEN
CNT 12
E
RBLK
REN
=
FULL
ESTOP
AFVAL
AFULL
AEVAL
AEMPTY
EMPTY
CNT 12
E
SUB 12
WBLK
WEN
=
FSTOP
Reset
Figure 2-46 • Fusion RAM Block with Embedded FIFO Controller
Preliminary v1.7
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