Actel Fusion Mixed-Signal FPGAs
Table 2-51 • ACM Address Decode Table for Analog Quad (continued)
ACMADDR [7:0] in
Decimal
Associated
Peripheral
Name
Description
73
MATCHREG1
MATCHREG2
MATCHREG3
MATCHREG4
MATCHBITS0
MATCHBITS1
MATCHBITS2
MATCHBITS3
MATCHBITS4
CTRL_STAT
Match register bits 15:8
Match register bits 23:16
Match register bits 31:24
Match register bits 39:32
Individual match bits 7:0
Individual match bits 15:8
Individual match bits 23:16
Individual match bits 31:24
Individual match bits 39:32
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
74
75
76
80
81
82
83
84
88
Control (write) / Status (read)
register bits 7:0
89
TEST_REG
Test register(s)
RTC
Note: ACMADDR bytes 1 to 40 pertain to the Analog Quads; bytes 64 to 89 pertain to the RTC.
1
ACM Characteristics
ACMCLK
tSUEACM
tHEACM
ACMWEN
ACMWDATA
ACMADDRESS
tSUDACM
tHDACM
D0
D1
A1
tSUAACM
tHAACM
A0
Figure 2-89 • ACM Write Waveform
tMPWCLKACM
ACMCLK
ACMADDRESS
ACMRDATA
A0
A1
tCLKQACM
RD0
RD1
Figure 2-90 • ACM Read Waveform
1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the
rc_osc, byte_en, and aq_wen signals have no impact.
Preliminary v1.7
2-125
ACTEL [ Actel Corporation ]
