Actel Fusion Mixed-Signal FPGAs
Timing Characteristics
Table 2-35 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std.
1.79
0.00
0.26
0.00
0.25
0.00
2.90
1.26
2.30
2.18
8.29
2.27
8.20
1.23
1.23
0.38
2.01
0.29
4.32
231
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REN_B, WEN_B Setup time
1.34
0.00
0.19
0.00
0.18
0.00
2.17
0.94
1.72
1.63
6.19
1.69
6.13
0.92
0.92
0.29
1.50
0.21
3.23
310
1.52
0.00
0.22
0.00
0.21
0.00
2.47
1.07
1.96
1.86
7.05
1.93
6.98
1.05
1.05
0.33
1.71
0.24
3.68
272
tENH
REN_B, WEN_B Hold time
tBKS
BLK_B Setup time
tBKH
BLK_B Hold time
tDS
Input data (DI) Setup time
tDH
Input data (DI) Hold time
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on DO (flow-through)
Clock High to New Data Valid on DO (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET_B Low to Empty/Full Flag Valid
RESET_B Low to Almost-Empty/Full Flag Valid
RESET_B Low to Data out Low on DO (flow-through)
RESET_B Low to Data out Low on DO (pipelined)
RESET_B Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle time
FMAX
Maximum Frequency for FIFO
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-7 on page 3-9 for derating
values.
Preliminary v1.7
2-79
ACTEL [ Actel Corporation ]
