Actel Fusion Mixed-Signal FPGAs
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the
EMPTY flag goes HIGH). A HIGH on this signal inhibits the counting.
FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the
FULL flag goes HIGH). A HIGH on this signal inhibits the counting.
For more information on these signals, refer to the "ESTOP and FSTOP Usage" section on
page 2-76.
FULL, EMPTY
When the FIFO is full and no more data can be written, the FULL flag asserts HIGH. The FULL flag is
synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to
prevent overflows. Since the write address is compared to a resynchronized (and thus time-
delayed) version of the read address, the FULL flag will remain asserted until two WCLK active
edges after a read operation eliminates the full condition.
When the FIFO is empty and no more data can be read, the EMPTY flag asserts HIGH. The EMPTY
flag is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition
and to prevent underflows. Since the read address is compared to a resynchronized (and thus time-
delayed) version of the write address, the EMPTY flag will remain asserted until two RCLK active
edges after a write operation removes the empty condition.
For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on
page 2-76.
AFULL, AEMPTY
These are programmable flags and will be asserted on the threshold specified by AFVAL and
AEVAL, respectively.
When the number of words stored in the FIFO reaches the amount specified by AEVAL while
reading, the AEMPTY output will go HIGH. Likewise, when the number of words stored in the FIFO
reaches the amount specified by AFVAL while writing, the AFULL output will go HIGH.
Preliminary v1.7
2-75
ACTEL [ Actel Corporation ]
