Actel Fusion Mixed-Signal FPGAs
VAREF
GNDREF
AV0
AC0
AT0
DAVOUT0
DACOUT0
DATOUT0
AV9
AC9
AT9
DAVOUT9
DACOUT9
DATOUT9
ATRETURN01
AG0
AG1
ATRETURN9
DENAV0
DENAC0
DENAT0
AG9
DENAV0
DENAC0
DENAT0
CMSTB0
CSMTB9
GDON0
GDON9
TMSTB0
TMSTB9
MODE[3:0]
TVC[7:0]
STC[7:0]
BUSY
CALIBRATE
DATAVALID
SAMPLE
CHNUMBER[4:0]
TMSTINT
RESULT[11:0]
RTCMATCH
RTCXTLMODE
RTCXTLSEL
ADCSTART
VAREFSEL
PWRDWN
ADCRESET
RTCPSMMATCH
RTCCLK
SYSCLK
ACMWEN
ACMRESET
ACMWDATA
ACMADDR
ACMCLK
ACMRDATA[7:0]
AB
Figure 2-64 • Analog Block Macro
Preliminary v1.7
2-81