A32200DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad to Y
Input Latch Gate-to-Output
Input Latch Hold
1.9
4.6
2.6
6.0
ns
ns
ns
ns
ns
0.0
0.7
6.1
0.0
0.9
8.1
tINSU
tILA
Input Latch Setup
Latch Active Pulse Width
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD5
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.6
3.4
4.6
5.4
7.0
3.5
4.6
6.1
7.2
9.3
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input Low to High
FO=32
FO=635
7.3
8.5
9.8
11.3
ns
ns
tCKL
Input High to Low
FO=32
FO=635
7.2
9.3
9.6
12.5
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO=32
FO=635
3.2
3.9
4.3
5.2
ns
ns
FO=32
FO=635
3.2
3.9
4.3
5.2
ns
ns
FO=32
FO=635
1.8
1.8
2.4
2.4
ns
ns
Input Latch External Setup
Input Latch External Hold
Minimum Period (1/fmax)
Maximum Datapath Frequency
FO=32
FO=635
0.0
0.0
0.0
0.0
ns
ns
FO=32
FO=635
3.0
3.8
4.0
5.1
ns
ns
FO=32
FO=635
5.8
6.8
7.7
9.1
ns
ns
fHMAX
Note:
FO=32
FO=635
172
147
130
110
MHz
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
54
ACTEL [ Actel Corporation ]
