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5962-0421901QUA 参数 Datasheet PDF下载

5962-0421901QUA图片预览
型号: 5962-0421901QUA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 250000 Gates, CMOS, CPGA624, CERAMIC, CGA-624]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX B  
B.3.3 Validation (certification). Validation of a manufacturing line for production of integrated circuits for use in space systems  
shall be accomplished by a team headed by DLA Land and Maritime with members from the space community (e.g., NASA, NRO,  
DTRA, and AFSMC), other interested services, and the customer as necessary.  
B.3.4 Manufacturing verification. When specified, the manufacturing verification procedure for new technology shall include  
characterization of actual devices at -55°C and 125°C (or high and low temperature as specified in the device specification) with DC,  
AC and full functional electrical parameters. Life testing of new technologies shall be determined by the manufacturer based on  
characterization with full temperature testing and read and record measurements every 1000 hours. Characterization shall also  
include a complete evaluation of potential failure mechanisms and mitigations strategies, calculation/evaluation of activation energy  
and acceleration factors for voltage and temperature, and establishment of long term reliability failure rates. The life test may be  
modified based on the determination of failure mechanisms and activation energy (see TM 1016 for guidance with a goal of 15 year  
operating life at +65°C TJ 95°C. The manufacturer shall determine worst case for their devices). Additional requirements for  
characterization are included in appendices G and H (see H.3.1.9 c (v)), and are a requirement for class V and class Y (class level S)  
devices.  
B.3.5 Design verification. When specified, a fully functional VHSIC Hardware Description Language (VHDL) model shall be  
available.  
B.3.6 Part or identifying number (PIN). Each class V and class Y level QML microcircuit shall be marked with the device class  
designator "V" or “Y” in place of the "Q" designator in the PIN format, see 3.6.2a herein. Devices procured to MIL-M-38510 PINs  
shall be marked in the format in 3.6.2b herein with the device class designator "S".  
B.3.7 Serialization. Prior to the first recorded electrical measurement in screening, each class V and class Y microcircuit shall be  
marked with a unique serial number assigned within the level of the individual microcircuit within that inspection lot.  
B.3.8 Traceability. For class V and class Y, inspection lot records shall be maintained to provide traceability from the device serial  
number to the specific wafer lot or to the specific wafer when testing to any group E subgroup (see table C-I), is performed on a wafer  
by wafer basis.  
B.3.9 New technology requirement. For class level S product, this is a product family, material, or process that has never been  
previously characterized and qualified by the manufacturer for space applications, and is detailed in the manufacturer’s new  
technology insertion program (see 3.4.1.1 and 6.4.42). Existing devices that meet the major change criteria of table A-I are to be  
evaluated in conjunction with the qualifying activity to determine if the change should be classified as a new technology, as defined in  
3.4.1.1 prior to finalized qualification plan implementation.  
B.3.10 Package integrity demonstration test plan (PIDTP) . Manufacturability, test, quality and reliability issues unique to specific  
non-traditional assembly/package technologies intended for space applications must be addressed in a PIDTP at the start of the  
package design cycle. The PIDTP shall be approved by QA after consultation with the space community. The technologies requiring  
such a plan are: a) non-hermetic packages (e.g., class Y), b) flip-chip assembly, and c) solder terminations. Microcircuits employing  
more than one of these technologies shall include elements for each in the PIDTP (see H.3.4.4.1).  
B.3.11 Solder terminated microcircuits. Microcircuits employing solder terminations (e.g., Ball Grid Array-BGA or Column Grid  
Array- CGA) shall meet all applicable appendices and Appendix B herein and must be addressed in the package integrity  
demonstration test plan (PIDTP) (see H.3.4.4.1.3).  
B.3.12 Assembly materials. For BGA and CGA packages material contents for solder balls, bumps and solder columns shall be  
specified on device SMDs and QM plan (see H.3.4.4.1.3) and organic materials shall be included in the PIDTP if applicable.  
B.3.13 Moisture sensitivity level (MSL) . Non-hermetic devices such as class Y can exhibit sensitivity to moisture-induced  
stress and must be handled, packaged, and stored in a proper manner to avoid potential damage during assembly  
solder reflow attachment and/or repair operations. Moisture sensitivity levels are defined as a rating identifying a  
component’s susceptibility to damage due to absorbed moisture when subjected to reflow soldering. The manufacturer  
shall be required to define the moisture sensitivity level (MSL) for each non-hermetic device in accordance with JEDEC  
J-STD-020.  
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