1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
X
Y
Z
U
M
T
See figure 1
See figure 1
See figure 1
See figure 1
See figure 1
See figure 1
See figure 1
352
624
624
256
1152
1152
624
Ceramic Quad Flat Pack
Ceramic Land Grid Array (LGA)
Ceramic Column Grid Array (CGA) 7/
Ceramic Quad Flat Pack
Ceramic Land Grid Array (LGA)
Ceramic Column Grid Array (CGA) 7/
Ceramic Column Grid Array (CGA) 7/
N
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings (for 1.5V/1.8V/2.5V/3.3V operating conditions). 8/
DC core supply voltage (V
) ........................................................ -0.3 to +1.7 V
) ............................................................ -0.3 to +3.75 V
CCA
DC I/O supply voltage (V
CCI
DC supply voltage for differential I/Os (V
) ................................ -0.3 to +3.75 V
CCDA
DC I/O reference voltage (V
DC external pump supply voltage (V
) ...................................................... -0.3 to +3.75 V
REF
) ...................................... -0.3 to +3.75 V
PUMP
Input voltage (V ) .............................................................................. -0.5 to +4.1 V 9/
I
Output voltage (V ) .......................................................................... -0.5 to +3.75 V
O
Storage temperature range (V
Lead temperature (soldering, 10 seconds) X and U .......................... 300oC
) .................................................. -65oC to +150oC
STG
Y, Z, T, M, and N............. 245C
Maximum junction temperature (T ) ................................................. 135oC
10/
J
Thermal resistance, junction-to-case (JC):
Case outline X ............................................................................... 0.2o C/W 11/ 14/
Case outlines Y, Z, and N .............................................................. 4.3o C/W 12/ 14/
Case outline U ............................................................................... 0.25oC/W 11/ 14/
Case outlines M and T .................................................................. 2.0o C/W 12/ 14/
Thermal resistance, junction-to-board (JB
)
Case outlines Z and N.................................................................... 3.5oC/W 13/ 14/
Case outline T................................................................................ 2.6C/W 13/ 14/
AC core supply transient voltage (VCCA) ........................................... -0.3 to +1.8 V 15/
7/ Case outlines T and N have a different solder composition than Z (see Figure 1 for details).
8/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
9/ Overshoot/Undershoot limits: For AC signals, the input signal may undershoot during transitions to -1.0 V for no longer
than 10% of the period or 11 ns whichever is smaller. Current during the transition must not exceed 95 mA. For AC
signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10% of the period or 11 ns
whichever is smaller. Current during the transition must not exceed 95 mA. Note: This specification does not apply to the
PCI standard. The PCI I/Os of this device are compliant to the PCI standard including the PCI overshoot/undershoot
specifications.
10/ Maximum junction temperature shall not be exceeded except for allowable short durations during burn-in screening
conditions in accordance with method 5004 of MIL-STD-883. Tj=135oC applies with wafer lot numbers starting with D2xxxx.
For older wafer lot numbers starting with D1xxxx , the Tj=125oC still applies.
11/ JC for case outlines X and U refers to the thermal resistance between the junction and the bottom of the package.
12/ JC for case outlines Y, Z, M, T, and N refers to the thermal resistance between the junction and the top of the package
(surface of the metal lid).
13/ JB for case outlines Z, T, and N refers to the thermal resistance between the junction and the tips of the solder columns
(where the device is attached to the circuit board).
14/ All thermal resistance data are obtained through simulation with computational fluid dynamic software. For case outlines Z,
T, and N, the JB is simulated with 4L/2P SMT board per JESD51.
15/ AC transient VCCA limit is for radiation induced transients less than 10s duration, and not intended for repetitive use. Core
voltage spikes from a single event transient will not negatively affect the reliability of the device if, for this non-repetitive event,
the transient does not exceed 1.8 V at any time, and the total time that the transient exceeds 1.575 V does not exceed 10 s in
duration.
SIZE
STANDARD
5962-04221
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
C
3
DSCC FORM 2234
APR 97
ACTEL [ Actel Corporation ]
