Core3DES
Encryption
To begin the process of encrypting data, the following
inputs are set:
1. K[1:64] is set to the first of three cipher sub-keys
("ck1" in
to encrypt the data.
2. D[1:64] is set to the plaintext data ("d1" in
to be encrypted.
3. ED is set to logic '1'.
4. EN is set to logic '1'.
After 15 clock cycles of the EN input being held
continuously at a logic '1' value, the KSEL[1:0] outputs
will change from '00' to '01', indicating that the second
of three cipher sub-keys (ck2 in
will need to be
presented on the K[1:64] inputs, which must be done by
the rising clock edge of the start of clock cycle 17 (one
complete clock cycle of slack is built into the Core3DES
circuitry). After 31 clock cycles of the EN input being held
at a logic '1', the KSEL[1:0] outputs will change from '01'
to '10', indicating that the third of three cipher sub-keys
...
(ck3 in
will need to be presented on the K[1:64]
inputs, which must be done by the rising clock edge of
the start of clock cycle 33.
After 48 clock cycles of the EN input being held
continuously at a logic '1' value, the QVAL signal will
transition from logic '0' to logic '1' and remain valid for
one clock cycle, indicating that valid ciphertext
(encrypted) data (q1 in
is available on the
Q[1:64] outputs. Note that the encrypted data is only
available during clock cycle 48, thus the user must
register or latch the data on Q[1:64], using the QVAL
signal as a qualifying register enable or latch enable.
As shown in
continuous encryption is possible.
For example, the second 64-bit plaintext data word (d2
in
can be immediately encrypted by presenting
d2 on the D[1:64] inputs by the rising clock edge of clock
cycle 49 and by presenting the cipher sub-keys ck1, ck2,
and ck3 in the sequence described earlier in this section.
cycle
1
2
15
16
17
18
...
31
32
33
34
...
47
48
49
50
CLK
K[1:64]
ck1
ck2
ck3
ck1
D[1:64]
d1
d2
ED
EN
KSEL[1:0]
00
00
01
01
10
10
00
Q[1:64]
QVAL
q1
Don't care
Figure 8 •
Example Encryption Sequence
Undefined
v5.0
7
ACTEL [ Actel Corporation ]
