Core3DES
Design Security
shows a typical system diagram. Note
that the cipher key, which is the "secret" key,
can be made up of FPGA logic cells, preventing the
possibility of design or data theft. Actel Flash-based
devices (ProASIC
PLUS
) use FlashLock™ technology, and
Actel antifuse-based devices (Axcelerator, SX-A, RTSX-S)
Actel FPGA
employ FuseLock™ technology, each of which provides a
means to keep the cipher key and the rest of the logic
secure. The output of the Core3DES macro should be
connected to registers or FIFOs, since it is only valid for
one clock cycle, as shown by example in the
and the
8.
Local Device
Plaintext
(unencrypted)
Data
Source
Registers or
FIFO
Other
Logic
Core3DES
Other
Logic
To other logic or
global distribution,
e.g., Internet, etc.
Encrypted
Data
Output
Cipher
Key
Figure 5 •
Typical Core3DES System
Core3DES Device Requirements
The Core3DES macro has been implemented in several Actel device families.
lists a summary of the
implementation data.
Table 1 •
Core3DES Device Utilization and Performance
Cells or Tiles
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
SX-A
RTSX-S
Sequential
156
156
150
152
152
152
152
Combinatorial
1257
1257
1456
620
620
640
640
Total
1413
1413
1606
772
772
792
792
Utilization
Device
AFS600
A3PE600-2
APA075-STD
AX125-3
RTAX1000S-1
A54SX16A-3
RT54SX32S-2
Total
11%
11%
53%
39%
5%
55%
28%
Performance
75 MHz
75 MHz
50 MHz
125 MHz
81 MHz
100 MHz
60 MHz
Throughput
300 Mbps
300 Mbps
66.7 Mbps
166.7 Mbps
108 Mbps
133.3 Mbps
80 Mbps
Note:
Data in this table achieved using typical synthesis and layout settings
Data throughput is computed by taking the bit width of the data (64 bits), dividing by the number of cycles (48), and
multiplying by the clock rate (performance). The result is listed in Mbps (millions of bits per second).
4
v5.0
ACTEL [ Actel Corporation ]
