Core3DES
Clear/Abort
At any point in the process of encrypting or decrypting
data, the user can abort the current operation by setting
the CLR input to logic '1'. This will clear all current
calculations with the key schedule and data schedule
logic. The user can then immediately begin to use a
different cipher key and data input on the very next
cycle, as shown in Figure 11.
an encryption or decryption sequence. Immediately, the
user can stop the current operation simply by holding
the CLR input at a logic '1' value for at least one clock
cycle and immediately commence on the following clock
cycle with a new cipher key and/or new data. If the
Core3DES macro is integrated into a system containing a
processor, the processor may wish to abort the
encryption or decryption operation for some specific
event (e.g., low or failing power condition).
The clear/abort functionality is provided as another aid
to the user. An example of its use occurs when the user
wants to change the cipher key, possibly in the middle of
...
...
...
47 48 49 50
cycle
1
2
3
1
2
15 16 17 18
31 32 33 34
CLK
K[1:64]
D[1:64]
ED
ck1
d1
ck1'
d2
ck2'
ck3'
ck1'
d3
EN
CLR
00
00 01
01 10
10 00
KSEL[1:0]
q2
Q[1:64]
QVAL
encrypted data using cipher
keys (ck1', ck2', ck3') and data (d2)
internal logic cleared/flushed;
cipher key (ck1) and data (d1)
calculations aborted
Undefined
Don't care
Figure 11 • Example Encryption Abort Sequence
Modes of Operation
Core3DES is implemented using the TECB (TDEA
Electronic Codebook) mode of operation, per ANSI
Standard X9.52. Depending upon the application, other
modes of operation for Triple DES may be desirable. For
this reason, Actel provides example VHDL and Verilog
source code for the TCBC (TDEA Cipher Block Chaining),
TCFB (TDEA Cipher Feedback), and TOFB (TDEA Output
Feedback) modes. For detailed information on specific
modes of operation, refer to ANSI Standard X9.52.
10
v5.0
ACTEL [ Actel Corporation ]
