ADDR1600C4G11
DDR3L-1600(CL11) 240-Pin R-DIMM
4GB(512M x 72-bits)
Timing Parameters:
Symbol
AC Characteristics Parameter
Min
Max
Unit
tCK(DLL_OFF) Minimum Clock Cycle Time (DLL off mode)
8
-
ns
tCH(avg)
tCL(avg)
tDQSQ
tQH
Average high pulse width
0.47
0.47
-
0.53
0.53
125
-
tCK(avg)
tCK(avg)
ps
Average low pulse width
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac)
levels
0.38
tCK(avg)
tDS(base)
tDH(base)
30
65
-
-
ps
ps
Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc)
levels
tDIPW
tRPRE
tRPST
tQSH
DQ and DM Input pulse width for each input
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
DQS, DQS# rising edge output access time from rising CK,
CK#
400
0.9
-
-
-
-
-
-
-
ps
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
0.3
0.40
0.40
0.9
tQSL
tWPRE
tWPST
0.3
tDQSCK
-255
255
ps
tLZ
tHZ
DQ, DQS and DQS# low-impedance time
DQ, DQS and DQS# high-impedance time
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
DQS, DQS# falling edge setup time to CK, CK# rising edge
DQS, DQS# falling edge hold time from CK, CK# rising edge
Internal READ Command to PRECHARGE Command delay
Delay from start of internal write transaction to internal read
command
-500
250
250
0.55
0.55
0.25
-
ps
-
ps
tDQSL
tDQSH
tDQSS
tDSS
tDSH
tRTP
0.45
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
-
0.45
-0.25
0.2
0.2
-
max(4nCK,7.5ns)
-
tWTR
max(4nCK,7.5ns)
-
-
tWR
tMRD
WRITE recovery time
15
4
-
-
-
ns
nCK
ps
Mode Register Set command cycle time
Command and Address setup time to CK, CK# referenced to
tIS(base)
65
13
ADATA [ ADATA Technology Co., Ltd. ]
