VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
A.C Characteristics: (6)(7)(8)(10)
(VDD=3.3V ±0.3V , VSS=0V, Ta=0 to 70°C)
Symbol
A.C. Parameter
-6
-7
-8
Unit
Note
Min
Max
Min
Max
Min
Max
t
t
t
t
Clock high time
Clock low time
2.5
2.5
3
CH
CL
T
ns
2.5
0.5
6
2.5
0.5
7
3
0.5
8
Transition time (Rise and Fall)
Clock cycle time CL* = 3
10
10
10
CK3
t
CL* = 2
8
10
12
CK2
t
t
t
t
t
t
t
t
Address/Control Input setup time
Address/Control Input hold time
Data Input setup time
1.5
1
1.75
1
2
1
2
1
1
IS
IH
1.5
1
1.75
1
DS
DH
LZ
Data Input hold time
Data output low impedance
Data output high imped- CL* = 3
1
1
5.5
6
5.5
7
6
7
6
9
9
HZ3
HZ2
AC3
ance
CL* = 2
Access time from CLK
(positive edge)
CL* = 3
CL* = 2
5.5
6
t
6
7
7
AC2
t
t
t
t
t
t
t
Data output hold time
RAS to CAS delay
2.3
18
12
1
2.5
20
14
1
2.5
20
16
1
OH
RCD
RRD
CCD
DPL
RAS
RP
Row activate to row activate delay
CAS to CAS Delay time
CLK
CLK
ns
Last data in to precharge
2
2
2
Row activate to precharge time
36 100,000 42 100,000 48 100,000
Precharge to refresh/row activate
command
3
3
3
CLK
t
t
t
t
t
t
t
t
Data-in to ACT (REF) Command (CL = 3)
Data-in to ACT (REF) Command (CL = 2)
Row cycle time
5
5
5
5
5
5
CLK
CLK
ns
DAL3
DAL2
RC
54
2
63
2
72
2
Mode Register Set Cycle time
Refresh time
CLK
ms
RSC
REF
SRX
BDL
PDE
64
64
64
Minimum CKE ”High”for Self-Refresh exit
Last data in to burst STOP command
Power Down Exit set-up time
1
1
1
1
1
1
1
1
1
CLK
CLK
CLK
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK
and tRC
.
.
4. These parameters depend on the output loading. Specified values are obtained with the outputs open.
5. Assume minimum column address update cycle tCCD (min).
Document:1G5-0189
Rev.1
Page6
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
