VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
IDD Specifications (VDD = 3.3V ±0.3V, TA = 0 ~ 70°C)
-6
-7
-8
Unit Note
Description/test condition
Operating Current
Symbol
Min
Max
Min
Max
Min
Max
IDD1
115
105
95
3,4
t
³ t
, outputs open
RC
RC(min)
Address changed once during tCK(min)
.
Burst length = 1 (One bank active)
Precharge Standby Current in non power-down
mode
IDD2N
40
35
40
35
40
35
3
CKE ³ VIH (min), CS ³ V (min), tCK =tCK(min)
IH
Input signals are changed once during 2 clocks
Precharge Standby Current in non power-down
mode
IDD2NS
mA
CLK £ VIL
CKE ³ VIH (min), tCK = ¥ ,
(max)
Input signals are stable
Precharge Standby Current in power-down mode
IDD2P
2
2
2
2
2
2
CKE £ VIL (max), tCK = tCK(min)
Precharge Standby Current in power-down mode
IDD2PS
CKE £ VIL (max), tCK = ¥ , CLK £ VIL
(max)
Active Standby Current in non power-down mode
CKE ³ VIH (min), CS ³ VIH(min), tCK = tCK(min)
Input signals are changed once during 2 clocks
IDD3N
50
40
50
40
50
40
3
Active Standby Current in non power-down mode
IDD3NS
CKE ³ VIH (min), tCK = ¥ , CLK £ VIL
(max)
Input signals are stable
Active Standby Current in power-down mode
IDD3P
35
35
35
35
35
35
CKE £ VIL (max), tCK = tCK(min)
Active Standby Current in power-down mode
IDD3PS
CKE £ VIL (max), tCK =¥ , CLK £ VIL
(max)
Operating Current
(Page burst, and all banks activated)
tCCD = tCCD(min), outputs open, gapless data
IDD4
150
140
130
4,5
3
Refresh Current
tRC ³ tRC (min) (tREF = 64ms)
IDD5
100
1
90
1
80
1
Self Refresh Current
IDD6
CKE £ 0.2V
Document:1G5-0189
Rev.1
Page5
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
