Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ and WFR
SCLK (output)
D7
D6
D5
D4
D3
D2
BUSY
READY
SDATA (out/in)
(From 6520)
(From EEPROM)
(LoZ)
(HiZ)
SDATA output Z
BUSY (bit)
Figure 15: 3-Wire Interface. Write Command when HiZ=1 and WFR=1.
1.5.15 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
locations. It is also able to send commands to the MPU. The interface to the slave port consists of the
PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD segment driver pins SEG3
to SEG6. The port pins default to LCD driver pins. The port is enabled by setting the SPE bit.
Access to I/O RAM (Configuration RAM) should not be attempted via the SPI Port.
A typical SPI transaction is as follows. While PCSZ is high, the port is held in an initialized/reset state.
During this state, PSDO is held in HiZ state and all transitions on PCLK and PSDI are ignored. When
PCSZ falls, the port will begin the transaction on the first rising edge of PCLK. A transaction consists of
an 8-bit command, a 16-bit address and then one or more bytes of data. The transaction ends when
PCSZ is raised. Some transactions may consist of a command only.
The last SPI command and address (if part of the command) are available to the MPU in registers
SP_CMD and SP_ADDR.
The SPI port supports data transfers at 1 Mb/s in mission mode and 16 kb/s in brownout mode. The SPI
commands are described in Table 45 and in Figure 16 illustrate the SPI Interface read and write timing.
Table 45: SPI Command Description
Command
Description
11xx xxxx ADDR Byte0 ... ByteN Read data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP__CMD=11xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1100 0000. Other-
wise, an SPI interrupt is generated.
10xx xxxx ADDR Byte0 ... ByteN Write data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP_CMD=10xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1000 0000. Other-
wise, an SPI interrupt is generated.
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