PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
Output Frequency and Output Divider Table (ICS525-07)
Output Frequency Range (MHz)
S2
S1
S0 CLKOutput
VDD = 2.5 V
VDD = 1.8 V
Pin 5 Pin 4 Pin 3
Divider
Min
8.3
Max
Min
Max
20.8
125
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
12
2
20.8
125
8.3
50
50
16
4
6.25
25
15.63
62.5
50
6.25
25
15.63
62.5
50
5
20
20
7
14.3
100
33.3
35.7
250
14.3
100
33.3
35.7
250
1
3
83.33
83.33
Output Frequency and Output Divider Table (ICS525-08)
Output Frequency Range (MHz)
S3
S2
S1
S0 CLKOutput
VDD = 2.5 V
VDD = 1.8 V
Pin 2 Pin 5 Pin 4 Pin 3
Divider
Min
23.9
15.9
11.9
9.5
6.8
6.0
5.3
4.8
4.3
3.7
3.4
3.2
2.8
2.5
1.0
0.4
Max
Min
Max
200
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
200
200
23.9
15.9
11.9
9.5
6.8
6.0
5.3
4.8
4.3
3.7
3.4
3.2
2.8
2.5
1.0
0.4
200
4
200
200
5
158.4
113.1
99.0
88.0
79.2
72.0
60.9
56.6
52.8
46.6
41.7
16.5
6.2
158.4
113.1
99.0
88.0
79.2
72.0
60.9
56.6
52.8
46.6
41.7
16.5
6.2
7
8
9
10
11
13
14
15
17
19
48
128
MDS 525-07/08 A
4
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com