PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
Pin Assignment (ICS525-07)
R5
R6
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
2
R3
S0
3
R2
S1
4
R1
S2
5
R0
VDD
X1/ICLK
X2
6
VDD
REF
CLK
GND
PD
V8
7
8
GND
V0
9
10
11
12
13
14
V1
V2
V7
V3
V6
V4
V5
Pin Descriptions (ICS525-07)
Pin
Number
Pin
Name
Pin
Type
Pin Description
Reference divider word input pins.
1, 2,
24-28
R5, R6,
R0-R4
I(PU)
3, 4, 5
6, 23
7
S0, S1, S2
VDD
I(PU)
Power
X1
Select pins for output divider. See table on page 4.
Connect to VDD.
X1/ICLK
X2
Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.
Crystal connection. Connect to a crystal or leave unconnected for clock.
Connect to ground.
8
X2
9, 20
10 - 18
19
GND
Power
I(PU)
Input
Output
Output
V0 - V8
PD
VCO divider word input pins.
Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.
PLL output clock.
21
CLK
22
REF
Reference output. Buffered crystal oscillator (or clock) output.
KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections
MDS 525-07/08 A
2
Revision 101105
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