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CYW311OXC 参数 Datasheet PDF下载

CYW311OXC图片预览
型号: CYW311OXC
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的VIA ™PRO -266 DDR芯片组 [FTG for VIA⑩ Pro-266 DDR Chipset]
分类和应用: 双倍数据速率
文件页数/大小: 18 页 / 250 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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W311  
Byte 3: Control Register  
Bit  
Bit 7  
Pin#  
--  
Name  
Reserved  
Default  
Description  
0
0
Reserved  
Bit 6  
7
SEL_48MHz  
0 = Select 24 MHz as output  
1 = Select 48 MHz as output (default).  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
6
7
48MHz  
24_48MHz  
PCI_F  
1
1
1
1
1
1
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
9
27  
26  
23  
AGP2  
AGP1  
AGP0  
Byte 4: Watchdog Timer Register  
Bit  
Pin#  
Name  
Default  
Description  
Bit 7  
-
PCI_Skew1  
0
PCI skew control  
00 = Normal  
01 = –500 ps  
10 = Reserved  
11 = +500 ps  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
-
PCI_Skew0  
0
These bits store the time-out value of the Watchdog  
Timer. The scale of the timer is determine by the pre  
scaler.  
The timer can support a value of 150 ms to 4.8 sec  
when the pre-scalar is set to 150 ms. If the pre-scaler  
is set to 2.5 sec, it can support a value from 2.5 sec  
to 80 sec.  
When the Watchdog Timer reaches to “0”, it will set  
the WD_To_STATUS bit and generate Reset if  
RST_EN_WD is enabled  
-
-
-
-
WD_TIMER4  
WD_TIMER3  
WD_TIMER2  
WD_TIMER1  
1
1
1
1
Bit 0  
-
WD_TIMER0  
1
0 = 150 ms  
1 = 2.5 sec  
Byte 5: Control Register 5  
Bit  
Pin#  
6
Name  
Default  
Description  
0 = Norm, 1 = High Drive  
0 = Norm, 1 = High Drive  
(Active/Inactive)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
48Mhz_DRV  
1
1
1
1
0
0
1
1
7
24_48MHz_DRV  
APIC1  
44  
45  
-
APIC0  
(Active/Inactive)  
Reserved  
Reserved  
REF1  
Reserved  
-
Reserved  
47  
48  
(Active/Inactive)  
REF0  
(Active/Inactive)  
Rev 1.0,November 25, 2006  
Page 6 of 18