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CYW311OXC 参数 Datasheet PDF下载

CYW311OXC图片预览
型号: CYW311OXC
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的VIA ™PRO -266 DDR芯片组 [FTG for VIA⑩ Pro-266 DDR Chipset]
分类和应用: 双倍数据速率
文件页数/大小: 18 页 / 250 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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W311  
Pin Definitions  
Pin  
Type  
Pin Name  
Pin No.  
Pin Description  
RST#  
CPU1:3  
32  
39, 38, 35  
O System Reset Output: Open-drain system reset output.  
(open CPU Clock Output: Frequency is set by the FS0:4 input or through serial input  
drain) interface. The CPU1:3 outputs are gated by the CLK_STOP# input.  
O
CPU_STOP#  
PCI1:8  
34  
I
CPU Output Control: 3.3V LVTTL-compatible input that stop CPU1:3.  
10, 11, 13,  
14, 16, 17,  
18, 20  
O
PCI Clock Outputs 1 through 8: Frequency is set by FS0:4 inputs or through  
serial input interface; see Table 5 for details. PCI1:8 outputs are gated by the  
PCI_STOP# input.  
PCI_STOP#  
PCI_F  
33  
9
O
O
PCI_STOP# Input: 3.3V LVTTL-compatible input that stops PCI1:8.  
Free-Running PCI Clock Output: Frequency is set by FS0:4 inputs or through  
serial input interface; see Table 5 for details.  
FS0:1  
AGP0:2  
21, 22  
23, 26, 27  
I
O
Frequency Selection Inputs: Selects CPU clock frequency as shown in Table 1.  
AGP Clock Output: This pin serves as the select strap to determine device  
operating frequency as described in Table 5.  
APIC0:2  
48MHz/FS3  
45, 44, 42  
6
O
I/O  
APIC Clock Output: APIC clock outputs.  
48 MHz Output/Frequency Select 3: 48 MHz is provided in normal operation.  
In standard PC systems, this output can be used as the reference for the Universal  
Serial Bus host controller. This pin also serves as a power-on strap option to  
determine device operating frequency as described in Table 5.  
24_48MHz/  
FS2  
REF1/FS4  
7
47  
I/O  
I/O  
24_48 MHz Output/Frequency Select 2: In standard PC systems, this output  
can be used as the clock input for a Super I/O chip. The output frequency is  
controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz.  
This pin also serves as a power-on strap option to determine device operating  
frequency as described in Table 5.  
Reference Clock Output 1/Frequency Select 4: 3.3V 14.318 MHz output clock.  
This pin also serves as a power-on strap option to determine device operating  
frequency as described in Table 5.  
REF0  
SCLK  
SDATA  
X1  
48  
28  
29  
3
O
Reference Clock Output 0: 3.3V 14.318 MHz output clock.  
Clock pin for SMBus circuitry.  
I
I/O  
I
Data pin for SMBus circuitry.  
Crystal Connection or External Reference Frequency Input: This pin has dual  
functions. It can be used as an external 14.318 MHz crystal connection or as an  
external reference frequency input.  
X2  
41  
I
Crystal Connection: An input connection for an external 14.318 MHz crystal. If  
using an external reference, this pin must be left unconnected.  
VDD_REF,  
VDD_48MHz,  
VDD_PCI,  
1, 5,15, 24,  
31  
Power Connection: Power supply for core logic, PLL circuitry, PCI outputs,  
reference outputs, 48 MHz output, and 24-48 MHz output, connect to 3.3V supply.  
P
VDD_AGP,  
VDD_CORE  
VDD_CPU,  
VDD_APIC  
41, 46, 37  
P
Power Connection: Power supply for APIC and CPU output buffers, connect to  
2.5V.  
Rev 1.0,November 25, 2006  
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