W256
Figure 1 shows the differential clock directly terminated by a
120 : resistor.
VCC
VCC
VTR
60:
Device
Under
Test
)
)
Out
RT =120:
60
:
Receiver
Out
VCP
Figure 1. Differential Signal Using Direct Termination Resistor
Layout Example Single Voltage
+3.3V Supply or 2.5V Supply
FB
VDD
10 PF
0.005 PF
G
C1
C2
G
1
28
27
26
25
G
G
G
G
2
3
4
V
G
G
V
5
24
G
23
22
21
20
19
18
17
16
15
6
7
8
9
10
11
12
V
G
G
G
V
G
G
13
14
G
G
V
FB = Dale ILB1206 – 300 (300:ꢀ@ 100 MHz)
µF
µF
C2 = 0.005
Cermaic CapsC1 = 10–22
= VIA to GND plane layer
V =VIA to respective supply plane layer
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1 PF ceramic
Rev 1.0,November 25, 2006
Page 6 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
