W256
Switching Characteristics[4]
Parameter
Name
DDR Rising Edge Rate[4]
Test Conditions
Min.
Typ.
Max.
Unit
t3d
Measured between 20% to 80% of
output (Refer to Figure 1)
0.5
1.50
V/ns
t4d
DDR Falling Edge Rate[4]
Output to Output Skew[4]
Measured between 20% to 80% of
output (Refer to Figure 1)
0.5
1.50
V/ns
t5
t6
All outputs equally loaded
All outputs equally loaded
100
150
ps
ps
Output t4o Output Skew for
SDRAM[2]
t7
t8
SDRAM Buffer HH Prop. Delay[4] Input edge greater than 1 V/ns
SDRAM Buffer LLProp. Delay[4] Input edge greater than 1 V/ns
5
5
10
10
ns
ns
Switching Waveforms
Duty Cycle Timing
t
1
t
2
All Outputs Rise/Fall Time
3.3V
0V
2.4V
2.4V
0.4V
OUTPUT
0.4V
t
3
t
4
Output-Output Skew
OUTPUT
OUTPUT
t
5
SDRAM Buffer HH and LL Propagation Delay
1.5V
INPUT
1.5V
OUTPUT
t6
t7
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.
Rev 1.0,November 25, 2006
Page 5 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
