CY28SRC01
Table 3. Byte Read and Byte Write Protocol
18:11
19
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
18:11
19
Command Code – 8 bits
Acknowledge from slave
Repeated start
27:20
28
20
27:21
28
Slave address – 7 bits
Read
29
29
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0:Control Register 0
Bit
7
@Pup
Name
Description
0
1
Reserved
Reserved
6
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z),
1 = Enable
5
4
1
1
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z),
1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z)
1 = Enable
3
2
1
1
SRC[T/C]1
SRC [T/C]0
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Byte 1: Control Register 1
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
5
4
3
2
1
0
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
SRCT/C
Spread Spectrum Selection
‘0’ = –0.35%
‘1’ = –0.50%
6
5
4
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev 1.0,November 20, 2006
Page 3 of 9
SPECTRALINEAR [ SPECTRALINEAR INC ]
