CY28435
Pin Description (continued)
Pin No.
Name
Type
Description
53
54
FS_C/REF1
I/O, 3.3V-tolerant input for CPU frequency selection/Reference clock.
PD Selects test mode if pulled to VIHFS_C when VTT_PWRGD# is asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifica-
tions.
SRESET#/PCI0
O, PU 3.3V LVTTL output for Watchdog reset/33-MHz clock output.
When configured as SRESET# output this output becomes open drain type with a
high (>100 k:) internal pull-up resistor.
clock output buffers, can be individually enabled or disabled.
Frequency Select Pins (FS_[A:E])
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and
FS_E inputs prior to VTT_PWRGD# assertion (as seen by the
clock synthesizer). Upon VTT_PWRGD# being sampled LOW
by the clock chip (indicating processor VTT voltage is stable),
the clock chip samples the FS_A, FS_B, FS_C, FS_D, and
FS_E input values. For all logic levels of FS_A, FS_B, FS_C,
FS_D, and FS_E, VTT_PWRGD# employs a one-shot
functionality in that once a valid LOW on VTT_PWRGD# has
been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C,
FS_D, and FS_E transitions will be ignored, except in test
mode.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
FS_C is a three-level input. When sampled at a voltage greater
than 2.1V by VTTPWRGD#, the device will enter test mode as
selected by the voltage level on the FS_B input.
Serial Data Interface
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
Input Conditions
FS_C FS_B
Output Frequency
FS_D
FS_A
CPU
SRC
CPU PLL CPU M CPU N CPU N SRC PLL
SRC M
SRC N
SRC N
Gear
divider DEFAULT allowable
Gear
divider (not DEFAULT allowable
Constants
range for Constants changeable
range for
DAF
DAF
byuser)
FSEL_3 FSEL_2 FSEL_1 FSEL_0
(MHz)
(MHz)
(G)
60
200 200 - 266
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
30
40
60
60
63
60
60
63
60
63
63
60
63
60
60
62
200
200
175
200
200
175
200
212
211
167
211
200
167
207
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
30
30
30
30
30
30
30
30
30
30
30
30
30
30
60
60
60
60
60
60
60
60
60
60
60
60
60
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 167 - 266
200 167 - 266
133.3333333
166.6666667
200
60
60
266.6666667
333.3333333
400
80
120
120
30
100.952381
133.968254
167
40
60
200.952381
266.6666667
334
60
80
120
120
400.6451613
X
X
HIGH
HIGH
LOW
HIGH
X
X
Tristate
REF/N
Tristate
REF/N
Tristate Tristate Tristate Tristate
REF/N REF/N REF/N REF/N
Figure 1. CPU and SRC Frequency Select Tables
Rev 1.0,November 20, 2006
Page 3 of 22
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