CY28435
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
0
0
CPU[T/C]0
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
6
5
4
3
0
HW
1
TEST_MODE
FS_D
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
FS_D reflects the value of the FS_D pin sampled on power-up.
0 = FS_D was LOW during VTT_PWRGD# assertion
REF0
REF Output Drive Strength
0 = High, 1 = Low
1
PCI, PCIF and SRC clock SW PCI_STP# Function
outputs except those set 0 = SW PCI_STP# assert, 1= SW PCI_STP# deassert
to free running
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
1
0
HW
HW
HW
FS_C
FS_B
FS_A
FS_C Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was LOW during VTT_PWRGD# assertion
FS_B Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was LOW during VTT_PWRGD# assertion
FS_A Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was LOW during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
1
1
1
0
0
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
6
5
4
3
2
Vendor ID Bit 2
Vendor ID Bit 2
1
Vendor ID Bit 1
Vendor ID Bit 1
0
Vendor ID Bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
Description
7
0
CPU_SS
Spread Selection for CPU PLL
0: –0.5% (peak to peak)
1: –1.0% (peak to peak)
6
0
CPU_DWN_SS
Spread Selection for CPU PLL
0: Down spread.
1: Center spread
5
4
0
0
SRC_SS_OFF
SRC_SS
SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Spread Selection for SRC PLL
0: –0.5% (peak to peak)
1: –1.0% (peak to peak)
3
0
RESERVED
RESERVED, Set = 0
Rev 1.0,November 20, 2006
Page 7 of 22