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CY28435ZXCT 参数 Datasheet PDF下载

CY28435ZXCT图片预览
型号: CY28435ZXCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为英特尔的Grantsdale芯片组 [Clock Generator for Intel Grantsdale Chipset]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 22 页 / 200 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28435  
Pin Description  
Pin No.  
Name  
VDD_PCI  
VSS_PCI  
Type  
Description  
1,7  
PWR 3.3V power supply for outputs.  
GND Ground for outputs.  
2,6  
3,55,56  
4
DF/PCI  
I/O, SE 3.3V LVTTL input to enable Dynamic Frequency input/33-MHz clock output.  
FS_E/PCI4  
I/O,PU, 3.3V-tolerant input for CPU frequency selection/33-MHz clock.  
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.  
SE  
5
8
PCI  
O, SE 33-MHz clock.  
DF_EN/PCIF0  
I/O,SE, 3.3V LVTTL input to enable Dynamic Frequency input/33-MHz clock output.  
PD (sampled on the VTT_PWRGD# assertion).  
1 = Enable, 0 = Disable  
9
SRESET_EN/PCIF I/O,SE, 3.3V LVTTL input to enable Watchdog/33-MHz clocks.  
PD 1 = Enable, 0 = Disable  
1
10  
17  
PCIF2  
O, SE 33-MHz clocks.  
VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,  
FS_B, FS_C,FS_D and FS_E inputs. After VTT_PWRGD# (active LOW) assertion,  
this pin becomes a real-time input for asserting power down (active HIGH).  
11  
12  
18  
VDD_48  
USB48_0  
FS_A  
PWR 3.3V power supply for outputs.  
48-MHz clock output.  
O
I, PD 3.3V-tolerant input for CPU frequency selection.  
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.  
13  
VSS_48  
GND Ground for outputs.  
14,15  
16  
DOT96T, DOT96C O, DIF Fixed 96 MHz clock output.  
FS_B/USB48_1 I/O,PU, 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.  
SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.  
19,20,22,23, SRCT/C  
24,25,30,31,  
32,33,36, 35  
O, DIF Differential serial reference clocks. Outputs have overclocking capability.  
21,28,34  
26,27  
VDD_SRC  
PWR 3.3V power supply for outputs.  
SRC4_SATAT,  
SRC4_SATAC  
O, DIF Differential serial reference clock. Recommended output for SATA.  
29  
37  
38  
39  
VSS_SRC  
VDDA  
GND Ground for outputs.  
PWR 3.3V power supply for PLL.  
GND Ground for PLL.  
VSSA  
IREF  
I
A precision resistor is attached to this pin, which is connected to the internal  
current reference.  
42  
VDD_CPU  
PWR 3.3V power supply for outputs.  
O, DIF Differential CPU clock outputs.  
GND Ground for outputs.  
41,40,44,43 CPUT/C  
45  
46  
47  
48  
49  
50  
51  
52  
VSS_CPU  
SCLK  
I
SMBus-compatible SCLOCK.  
SMBus-compatible SDATA.  
SDATA  
I/O  
VDD_REF  
XOUT  
PWR 3.3V power supply for outputs.  
O, SE 14.318 MHz crystal output.  
XIN  
I
14.318 MHz crystal input.  
VSS_REF  
FS_D/REF0  
GND Ground for outputs.  
I/O, SE, 3.3V-tolerant input for CPU frequency selection/Reference clock.  
PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.  
Rev 1.0,November 20, 2006  
Page 2 of 22