CY28358
AC Parameters[8,9] (VDD = VDDQ = 2.5V 5%, TA = 0°C to +70°C)
Parameter
fCLK
Description
Operating Clock Frequency
Input Clock Duty Cycle
Conditions
Min.
60
Typ. Max.
Unit
MHz
%
200
60
tDC
40
tLOCK
tR/tF
tPZL,tPZH
Maximum PLL lock Time
100
2.5
Ps
Output Clocks Slew Rate
Output Enable Time[10]
(all outputs)
Output Disable Time[10]
(all outputs)
20% to 80% of VOD
1
V/ns
ns
3
3
tPLZ PHZ
,t
ns
tCCJ
Cycle to Cycle Jitter[12]
Half-period jitter[12]
f > 66 MHz
f > 66 MHz
–100
–100
1.5
100
100
6
ps
ps
ns
tjit(h-per)
tPLH
Low-to-High Propagation Delay, CLKIN
to CLKT[0:5]
3.5
3.5
tPHL
High-to-Low Propagation Delay, CLKIN
to CLKT[0:5]
1.5
6
ns
tSKEW
Any Output to Any Output Skew[11]
Phase Error[11]
100
150
50
ps
ps
ps
tPHASE
tPHASEJ
–150
–50
Phase Error Jitter
f > 66 MHz
Notes:
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 33.3kHz with a down
spread of –0.5%.
10. Refers to transition of non-inverting outpu.t
11. All differential input and output terminals are terminated with 120:/16pF as shown in Figure 7.
12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
Rev 1.0,November 20, 2006
Page 9 of 10
SPECTRALINEAR [ SPECTRALINEAR INC ]
