CY28358
Maximum Ratings[3]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD:.............. VDD + 0.3V
Storage Temperature: ................................ –65qC to + 150qC
Operating Temperature:.................................... 0qC to +85qC
Maximum Power Supply:................................................3.5V
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters[4] (VDDA = VDDQ = 2.5V + 5%, TA = 0qC to +70qC)
Parameter
VIL
Description
Input Low Voltage
Input High Voltage
Input Voltage Low
Input Voltage High
Input Current
Conditions
SDATA, SCLK
Min.
Typ.
Max.
Unit
V
1.0
VIH
VIL
VIH
IIN
SDATA, SCLK
CLKIN, FBIN
CLKIN, FBIN
2.2
V
0.4
10
V
2.1
V
VIN = 0V or VIN = VDDQ, CLKIN,
FBIN
–10
µA
IOL
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing[5}
VDDQ = 2.375V, VOUT = 1.2V
VDDQ = 2.375V, VOUT = 1V
VDDQ = 2.375V, IOL = 12 mA
VDDQ = 2.375V, IOH = –12 mA
26
35
mA
mA
V
IOH
–18
–32
VOL
VOH
VOUT
VOC
0.6
1.7
1.1
V
VDDQ–0.4
V
Output Crossing
Voltage[6]
(VDDQ/2) –
0.2
VDDQ/2
(VDDQ/2) + 0.2
V
IOZ
High-ImpedanceOutput VO = GND or VO = VDDQ
Current
–10
10
µA
IDDQ
Dynamic Supply
Current[7]
All VDDQ and VDDI
FO = 200 MHz
,
235
300
mA
IDSTAT
IDD
Static Supply Current
PLL Supply Current
Input Pin Capacitance
2
12
6
mA
mA
pF
VDDA only
9
4
CIN
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held high or low to prevent them from floating
5. For load conditions see Figure 7.
6. The value of V is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120: resistor. See Figure 7.
OC
7. All outputs switching loaded with 16pF in 60: environment. SeeFigure 7
Rev 1.0,November 20, 2006
Page 8 of 10
SPECTRALINEAR [ SPECTRALINEAR INC ]
