CY28358
Pin Description[1]
Pin
Name
CLKIN
FBIN
I/O
Description
Electrical Characteristics
8
I
I
Clock Input.
Input
20
Feedback Clock Input. Connect to FBOUT for Input
accessing the PLL.
2,4,13,17,24,26
1,5,14,16,25,27
19
CLKT(0:5)
CLKC(0:5)
FBOUT
O
O
O
Clock Outputs
Clock Outputs
Differential Outputs
Feedback Clock Output. Connect to FBIN for Output
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
7
SCLK
I
Serial Clock Input. Clocks data at SDATA into Data Input for the two line serial bus
the internal register.
22
SDATA
I/O Serial Data Input. Input data is clocked to the Data Input and Output for the two line
internal register to enable/disable individual
outputs. This provides flexibility in power
management.
serial bus
3,12,23
10
VDD
AVDD
GND
AGND
NC
2.5V Power Supply for Logic
2.5V Power Supply for PLL
Ground
2.5V Nominal
2.5V Nominal
6,15,28
11
Analog Ground for PLL
Not Connected
9, 18, 21
Function Table
Inputs
Outputs
CLKC(0:5)[2]
PLL
BYPASSED/OFF
VDDA
GND
CLKIN
CLKT(0:5)[2]
FBOUT
L
L
H
H
L
L
H
GND
H
BYPASSED/OFF
2.5V
L
H
L
H
L
On
On
Off
2.5V
H
L
H
2.5V
< 20 MHz
Hi-Z
Hi-Z
Hi-Z
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Zero Delay Buffer
When used as a zero delay buffer the CY28358 will likely be
in a nested clock tree application. For these applications the
CY28358 offers a clock input as a PLL reference. The
CY28358 then can lock onto the reference and translate with
near zero delay to low-skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
Power Management
The individual output enable/disable control of the CY28358
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when
disabled through the two-line interface as individual bits are
set low in Byte0 and Byte1 registers. The feedback output
FBOUT cannot be disabled via two line serial bus. The
enabling and disabling of individual outputs is done in such a
manner as to eliminate the possibility of partial “runt” clocks.
Notes:
1. A bypass capacitor (0.1PF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high
frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two line serial interface.
Rev 1.0,November 20, 2006
Page 2 of 10
SPECTRALINEAR [ SPECTRALINEAR INC ]
