CY28346
Byte 2: PCI Clock Control Register (all bits are Read and Write functional)
Bit
7
@Pup
Pin#
53
18
17
16
13
12
11
Description
REF Output Control. 0 = high strength, 1 = low strength.
PCI6 Output Control. 1 = enabled, 0 = forced LOW.
PCI5 Output Control. 1 = enabled, 0 = forced LOW.
PCI4 Output Control. 1 = enabled, 0 = forced LOW.
PCI3 Output Control. 1 = enabled, 0 = forced LOW.
PCI2 Output Control. 1 = enabled, 0 = forced LOW.
PCI1 Output Control. 1 = enabled, 0 = forced LOW.
PCI0 Output Control. 1 = enabled, 0 = forced LOW.
0
1
1
1
1
1
1
1
6
5
4
3
2
1
0
10
Byte 3: PCI_F Clock and 48M Control Register (all bits are Read and Write functional)
Bit
7
@Pup
Pin#
38
39
7
Description
48MDOT Output Control. 1 = enabled, 0 = forced LOW.
48MUSB Output Control. 1 = enabled, 0 = forced LOW.
1
1
0
0
0
1
1
1
6
5
PCI_STP#, Control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_STP#, Control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_STP#, Control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_F2 Output Control. 1 = running, 0 = forced LOW.
4
6
3
5
2
7
1
6
PCI_F1 Output Control. 1 = running, 0 = forced LOW.
0
5
PCI_F0 Output Control. 1 = running, 0 = forced LOW.
Byte 4: DRCG Control Register (all bits are Read and Write functional)
Bit @Pup Pin# Description
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
SS2 Spread Spectrum Control Bit (0 = down spread, 1 = center spread).
Reserved. Set = 0.
33 3V66_0 Output Enabled. 1 = enabled, 0 = disable.
35 3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled.
24 3V66_5 Output Enable. 1 = enabled, 0 = disabled.
23 66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled.
22 66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled.
21 66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled.
Byte 5: Clock Control Register (all bits are Read and Write functional)
Bit @Pup Pin# Description
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
SS1 Spread Spectrum Control Bit.
SS0 Spread Spectrum Control Bit.
66IN to 66M delay Control MSB.
66IN to 66M delay Control LSB.
Reserved. Set = 0.
48MDOT Edge Rate Control. When set to 1, the edge is slowed by 15%.
Reserved. Set = 0.
USB edge rate control. When set to 1, the edge is slowed by 15%.
Rev 1.0,November 24, 2006
Page 4 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
