CY28346
Output under Test
Probe
Load Cap
3.3V signals
tDC
-
-
3.3V
2.4V
1.5V
0.4V
0V
Tr
Tf
Figure 3. For Single-ended Output Signals
3. Series resistance in the buffer circuit—Ros (see Figure 4).
Buffer Characteristics
4. Current accuracy at given configuration into nominal test
load for given configuration.
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristics:
Iout is selectable depending on implementation. The param-
eters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviation from the expected output current is 7% as shown in
the current accuracy table.
1. Output impedance of the current mode buffer circuit—Ro
(see Figure 4).
2. Minimum and maximum required voltage operation range
of the circuit—Vop (see Figure 4).
VDD3 (3.3V +/- 5%)
Slope ~ 1/R0
Ro
Iout
Ros
0V
1.2V
Iout
Vout = 1.2V max
Vout
Figure 4. Buffer Characteristics
Rev 1.0,November 24, 2006
Page 7 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
